Thomas J. Snethen

13 papers A* 2A 5Journal 3Unranked 3

Year	Rank	Type	Title / Venue / Authors
2014	A	`conf`	Efficient testing of hierarchical core-based SOCs. ITC Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen
2010	A	`conf`	Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise
2009	J	`jnl`	Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. J. Low Power Electron. Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai
2007	A	`conf`	Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. ITC Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise
2007	—	`conf`	Using Programmable On-Product Clock Generation (OPCG) for Delay Test. ATS Brion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen
2001	—	`conf`	A SmartBIST Variant with Guaranteed Encoding. Asian Test Symposium Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater
1999	—	`conf`	A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor. Asian Test Symposium Xinghao Chen, Thomas J. Snethen, Joe Swenton, Ron Walther
1998	A	`conf`	Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip. ITC Mary P. Kusko, Bryan J. Robbins, Thomas J. Snethen, Peilin Song, Thomas G. Foote, William V. Huott
1997	J	`jnl`	Advanced microprocessor test strategy and methodology. IBM J. Res. Dev. William V. Huott, Timothy J. Koprowski, Bryan J. Robbins, Mary P. Kusko, Stephen Pateras, Dale E. Hoffman, Timothy G. McNamara, Thomas J. Snethen
1996	J	`jnl`	A weighted random pattern test generation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
1994	A	`conf`	Design of an Efficient Weighted-Random-Pattern Generation System. ITC Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
1977	A*	`conf`	Simulator-oriented fault test generator. DAC Thomas J. Snethen
1970	A*	`conf`	Minimizing the problem of logic testing by the interaction of a design group with user-oriented facilities. DAC Manuel Correia, Donald Cossman, Franco Putzolu, Thomas J. Snethen