| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2017 | J | jnl |
Nat.
|
| 2011 | A | conf |
An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations.
DATE
|
| 2007 | J | jnl |
Data Knowl. Eng.
|
| 2005 | J | jnl |
Data Knowl. Eng.
|
| 2000 | — | conf |
PATMOS
|
| 2000 | B | conf |
FPL
|
| 2000 | — | conf |
ASP-DAC
|
| 2000 | A | conf |
FPGA
|
| 1999 | B | conf |
FPL
|
| 1999 | — | conf |
HICSS
|
| 1999 | B | conf |
FPL
|
| 1999 | — | conf |
HICSS
|
| 1998 | B | conf |
FPL
|
| 1998 | — | conf |
IPPS/SPDP Workshops
|