Thomas Charles Wilson

19 papers A* 1C 1Misc 7Journal 5Unranked 5
YearRankTypeTitle / Venue / Authors
2004 Misc conf
Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees.
VLSI Design
Gary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji
2003 J jnl
An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors.
SIGARCH Comput. Archit. News
Gary Gréwal, Thomas Charles Wilson, Andrew Morton
2003 J jnl
Mapping Reference Code to Irregular DSPS within the Retargetable, Optimizing Compiler Cogen(T).
Int. J. Comput. Intell. Appl.
Gary William Grewal, Thomas Charles Wilson
2002 Misc conf
An Enhanced Genetic Algorithm Approach to the Channel Assignment Problem in Mobile Cellular Networks.
AI
Gary William Grewal, Thomas Charles Wilson, Christopher W. Nell
2001 J jnl
An Enhanced Genetic Algorithm for Solving the High-Level Synthesis Problems of Scheduling, Allocation, and Binding.
Int. J. Comput. Intell. Appl.
Gary William Grewal, Thomas Charles Wilson
2001 A* conf
Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T).
MICRO
Gary William Grewal, Thomas Charles Wilson
1997 Misc conf
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design.
VLSI Design
Gary William Grewal, Thomas Charles Wilson
1997 Misc conf
Shake And Bake: A Method of Mapping Code to Irregular DSPs.
VLSI Design
Thomas Charles Wilson, Gary William Grewal
1996 J jnl
A Modified Approach to Test Plan Generation for Combinational Logic Blocks.
VLSI Design
Anupam Basu, Dilip K. Banerji, Amit Basu, Thomas Charles Wilson, Jayanti C. Majithia
1996 Misc conf
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation.
VLSI Design
J. Shu, Thomas Charles Wilson, Dilip K. Banerji
1995 J jnl
An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis.
VLSI Design
Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji
1994 C conf
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis.
ICCD
Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji
1994 — conf
An ILP-based approach to code generation.
Code Generation for Embedded Processors
Thomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji
1994 — conf
An integrated approach to retargetable code generation.
HLSS
Thomas Charles Wilson, Gary Gréwal, Ben Halley, Dilip K. Banerji
1993 Misc conf
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis.
VLSI Design
Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji
1993 — conf
MinMux: a new approach for global minimization of multiplexers in interconnect synthesis.
Great Lakes Symposium on VLSI
Thomas Charles Wilson, Manoj K. Garg, R. Deadman, Ben Halley, Dilip K. Banerji
1992 Misc conf
An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test.
VLSI Design
Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia
1991 — conf
Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits.
Great Lakes Symposium on VLSI
Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia
1991 — conf
Test plan generation and concurrent scheduling of tests in the presence of conflicts.
Great Lakes Symposium on VLSI
Thomas Charles Wilson, Anupam Basu, Dilip K. Banerji, Jayanti C. Majithia