Thomas Carle

35 papers A 2B 4C 3Misc 3Journal 13Unranked 7
YearRankTypeTitle / Venue / Authors
2026 J jnl
Convolutions Predictable Offloading to an Accelerator: Formalization and Optimization.
CoRR
Benjamin Husson, Mohammed Belcaid, Thomas Carle, Claire Pagetti
2026 J jnl
Extension of ACETONE C code generator for multi-core architectures.
CoRR
Yanis Aït-Aïssa, Thomas Carle, Sergei Chichin, Benjamin Lesage, Claire Pagetti
2025 J jnl
Bounding the WCET of a GPU Thread Block with a Multi-Phase Representation of Warps Execution (Artifact).
Dagstuhl Artifacts Ser.
Louison Jeanmougin, Thomas Carle, Christine Rochange
2025 B conf
Bounding the WCET of a GPU Thread Block with a Multi-Phase Representation of Warps Execution.
ECRTS
Louison Jeanmougin, Thomas Carle, Christine Rochange
2024 — ed.
22nd International Workshop on Worst-Case Execution Time Analysis, WCET 2024, Lille, France, July 9, 2024
WCET
Thomas Carle
2024 A conf
A Predictable SIMD Library for GEMM Routines.
RTAS
Iryna De Albuquerque Silva, Thomas Carle, Adrien Gauffriau, Victor Jégu, Claire Pagetti
2024 C conf
Coordinating the Fetch and Issue Warp Schedulers to Increase the Timing Predictability of GPUs.
DSD
Noïc Crouzet, Thomas Carle, Christine Rochange
2024 Misc conf
Marmot: Extraction of Fine-Grain Memory Access Profiles for real-time software.
RTNS
Hector Chabot, Isabelle Puaut, Thomas Carle, Hugues Cassé
2024 C conf
Modelling and proving the monotonicity of processor pipelines in Coq.
MEMOCODE
Alban Gruin, Armelle Bonenfant, Thomas Carle, Christine Rochange
2024 J jnl
Multi-core interference over-estimation reduction by static scheduling of multi-phase tasks.
Real Time Syst.
Rémi Meunier, Thomas Carle, Thierry Monteil
2024 — book
Parallelism and timing predictability in real-time systems.
Thomas Carle
2024 C conf
Verifying HyperLTL Properties in Event-B.
ABZ
Jean-Paul Bodeveix, Thomas Carle, Elie Fares, Mamoun Filali, Thai Son Hoang
2023 J jnl
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhenyu Bai, Hugues Cassé, Thomas Carle, Christine Rochange
2023 Misc conf
Enabling timing predictability in the presence of store buffers.
RTNS
Alban Gruin, Thomas Carle, Christine Rochange, Pascal Sainrat
2023 J jnl
Extending a predictable machine learning framework with efficient gemm-based convolution routines.
Real Time Syst.
Iryna De Albuquerque Silva, Thomas Carle, Adrien Gauffriau, Claire Pagetti
2023 J jnl
MINOTAuR: A Timing Predictable RISC-V Core Featuring Speculative Execution.
IEEE Trans. Computers
Alban Gruin, Thomas Carle, Christine Rochange, Hugues Cassé, Pascal Sainrat
2023 — conf
Validation of Processor Timing Models Using Cycle-Accurate Timing Simulators.
WCET
Alban Gruin, Thomas Carle, Christine Rochange, Pascal Sainrat
2023 — conf
Warp-Level CFG Construction for GPU Kernel WCET Analysis.
WCET
Louison Jeanmougin, Pascal Sotin, Christine Rochange, Thomas Carle
2022 J jnl
A Framework for Calculating WCET Based on Execution Decision Diagrams.
ACM Trans. Embed. Comput. Syst.
Zhenyu Bai, Hugues Cassé, Marianne De Michiel, Thomas Carle, Christine Rochange
2022 J jnl
ACETONE: Predictable Programming Framework for ML Applications in Safety-Critical Systems (Artifact).
Dagstuhl Artifacts Ser.
Iryna De Albuquerque Silva, Thomas Carle, Adrien Gauffriau, Claire Pagetti
2022 B conf
ACETONE: Predictable Programming Framework for ML Applications in Safety-Critical Systems.
ECRTS
Iryna De Albuquerque Silva, Thomas Carle, Adrien Gauffriau, Claire Pagetti
2022 J jnl
Computing Execution Times with eXecution Decision Diagrams in the Presence of Out-Of-Order Resources.
CoRR
Zhenyu Bai, Hugues Cassé, Thomas Carle, Christine Rochange
2022 B conf
Correctness and Efficiency Criteria for the Multi-Phase Task Model.
ECRTS
Rémi Meunier, Thomas Carle, Thierry Monteil
2021 A conf
Speculative Execution and Timing Predictability in an Open Source RISC-V Core.
RTSS
Alban Gruin, Thomas Carle, Hugues Cassé, Christine Rochange
2021 — conf
Static Extraction of Memory Access Profiles for Multi-core Interference Analysis of Real-Time Tasks.
ARCS
Thomas Carle, Hugues Cassé
2021 J jnl
Static extraction of memory access profiles for multi-core interference analysis of real-time tasks.
CoRR
Thomas Carle, Hugues Cassé
2020 B conf
Improving the Performance of WCET Analysis in the Presence of Variable Latencies.
LCTES
Zhenyu Bai, Hugues Cassé, Marianne De Michiel, Thomas Carle, Christine Rochange
2018 — conf
Reducing Timing Interferences in Real-Time Applications Running on Multicore Architectures.
WCET
Thomas Carle, Hugues Cassé
2016 Misc conf
Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems.
CASES
Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar
2015 J jnl
From Dataflow Specification to Multiprocessor Partitioned Time-triggered Real-time Implementation.
Leibniz Trans. Embed. Syst.
Thomas Carle, Dumitru Potop-Butucaru, Yves Sorel, David Lesens
2015 — conf
On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling.
FORMATS
Raul Gorcitz, Emilien Kofman, Thomas Carle, Dumitru Potop-Butucaru, Robert de Simone
2014 — —
Compilation efficace de spécifications de contrôle embarqué avec prise en compte de propriétés fonctionnelles et non-fonctionnelles complexes. (Efficient compilation of embedded control specifications with complex functional and non-functional properties).
Thomas Carle
2014 J jnl
Predicate-aware, makespan-preserving software pipelining of scheduling tables.
ACM Trans. Archit. Code Optim.
Thomas Carle, Dumitru Potop-Butucaru
2014 — conf
Reconciling performance and predictability on a many-core through off-line mapping.
ReCoSoC
Thomas Carle, Manel Djemal, Daniela Genius, François Pêcheux, Dumitru Potop-Butucaru, Robert de Simone, Franck Wajsbürt, Zhen Zhang
2014 — conf
Static Mapping of Real-Time Applications onto Massively Parallel Processor Arrays.
ACSD
Thomas Carle, Manel Djemal, Dumitru Potop-Butucaru, Robert de Simone, Zhen Zhang