Thomas Canhao Xu

40 papers B 2C 7Misc 1Journal 10Unranked 20

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Deep Belief Network and Closed Polygonal Line for Lung Segmentation in Chest Radiographs. Comput. J. Tao Peng, Thomas Canhao Xu, Yihuai Wang, Fanzhang Li
2020	J	`jnl`	Hybrid Automatic Lung Segmentation on Chest CT Scans. IEEE Access Tao Peng, Thomas Canhao Xu, Yihuai Wang, Hailing Zhou, Sema Candemir, Wan Mimi Diyana Wan Zaki, Shanq-Jang Ruan, Jing Wang, Xinjian Chen
2019	J	`jnl`	Segmentation of Lung in Chest Radiographs Using Hull and Closed Polygonal Line Method. IEEE Access Tao Peng, Yihuai Wang, Thomas Canhao Xu, Xinjian Chen
2018	J	`jnl`	Detection of Lung Contour with Closed Principal Curve and Machine Learning. J. Digit. Imaging Tao Peng, Yihuai Wang, Thomas Canhao Xu, Lianmin Shi, Jianwu Jiang, Shilang Zhu
2017	J	`jnl`	PEN: a power law-enhanced network design for high efficiency multicore architecture. Concurr. Comput. Pract. Exp. Thomas Canhao Xu, Ville Leppänen
2016	B	`conf`	Analysing and Modelling the On-Chip Traffic of Parallel Applications. SEAA Thomas Canhao Xu, Jonne Pohjankukka, Ville Leppänen
2016	—	`conf`	LUTMap: A Dynamic Heuristic Application Mapping Algorithm Based on Lookup Tables. IDCS Thomas Canhao Xu, Ville Leppänen
2015	—	`conf`	Cache- and Communication-aware Application Mapping for Shared-cache Multicore Processors. ARCS Thomas Canhao Xu, Ville Leppänen
2015	—	`conf`	DBFS: Dual Best-First Search Mapping Algorithm for Shared-Cache Multicore Processors. ICA3PP (1) Thomas Canhao Xu, Ville Leppänen
2015	J	`jnl`	PDNOC: Partially diagonal network-on-chip for high efficiency multicore systems. Concurr. Comput. Pract. Exp. Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2015	—	`conf`	Parallel Applications and On-chip Traffic Distributions: Observation, Implication and Modelling. ICSOFT-EA Thomas Canhao Xu, Jonne Pohjankukka, Paavo Nevalainen, Ville Leppänen, Tapio Pahikkala
2015	—	`conf`	Trio: A Triple Class On-chip Network Design for Efficient Multicore Processors. HPCC/CSS/ICESS Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2014	—	`conf`	BDMap: A Heuristic Application Mapping Algorithm for the Big Data Era. UIC/ATC/ScalCom Thomas Canhao Xu, Jussi Toivonen, Tapio Pahikkala, Ville Leppänen
2014	C	`conf`	Exploration of a Heterogeneous Concentrated-Sparse On-Chip Interconnect for Energy Efficient Multicore Architecture. CIT Thomas Canhao Xu, Ville Leppänen, Martti Forsell
2014	C	`conf`	Mixed-Criticality Run-Time Task Mapping for NoC-Based Many-Core Systems. PDP Mohammad Fattah, Amir-Mohammad Rahmani, Thomas Canhao Xu, Anil Kanduri, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2013	C	`conf`	DSNOC: A Hybrid Dense-Sparse Network-on-Chip Architecture for Efficient Scalable Computing. DASC Thomas Canhao Xu, Ville Leppänen, Martti Forsell
2013	—	`conf`	Evaluate and optimize parallel Barnes-Hut algorithm for emerging many-core architectures. HPCS Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2013	—	`conf`	MMSoC: a multi-layer multi-core storage-on-chip design for systems with high integration. CompSysTech Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2013	B	`conf`	OPTNOC: An Optimized 3D Network-on-Chip Design for Fast Memory Access. PaCT Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2013	J	`jnl`	Optimal placement of vertical connections in 3D Network-on-Chip. J. Syst. Archit. Thomas Canhao Xu, Gert Schley, Pasi Liljeberg, Martin Radetzki, Juha Plosila, Hannu Tenhunen
2013	—	`conf`	Optimized multicore architectures for data parallel fast Fourier transform. CompSysTech Thomas Canhao Xu, Tapio Pahikkala, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2013	—	`conf`	PDNOC: An Efficient Partially Diagonal Network-on-Chip Design. PPAM (1) Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2012	—	`conf`	A high-efficiency low-cost heterogeneous 3D network-on-chip design. NoCArc@MICRO Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2012	—	`conf`	Exploration of heuristic scheduling algorithms for 3D multicore processors. Map2MPSoC/SCOPES Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2012	—	`conf`	Implementation and Analysis of Block Dense Matrix Decomposition on Network-on-Chips. HPCC-ICESS Thomas Canhao Xu, Tapio Pahikkala, Antti Airola, Pasi Liljeberg, Juha Plosila, Tapio Salakoski, Hannu Tenhunen
2012	J	`jnl`	Parallelized Online Regularized Least-Squares for Adaptive Embedded Systems. Int. J. Embed. Real Time Commun. Syst. Tapio Pahikkala, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen, Tapio Salakoski
2011	—	`conf`	A Minimal Average Accessing Time Scheduler for Multicore Processors. ICA3PP (2) Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen
2011	—	`conf`	A Parallel Online Regularized Least-squares Machine Learning Algorithm for Future Multi-core Processors. PECCS Tapio Pahikkala, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen, Tapio Salakoski
2011	J	`jnl`	A generic adaptive path-based routing method for MPSoCs. J. Syst. Archit. Masoud Daneshtalab, Masoumeh Ebrahimi, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen
2011	J	`jnl`	A study of 3D Network-on-Chip design for data parallel H.264 coding. Microprocess. Microsystems Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen
2011	C	`conf`	Change Function of 2D/3D Network-on-Chip. CIT Alexander Wei Yin, Thomas Canhao Xu, Bo Yang, Pasi Liljeberg, Hannu Tenhunen
2011	—	`conf`	Explorations of optimal core and cache placements for Chip Multiprocessor. NORCHIP Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen
2011	Misc	`conf`	Optimal memory controller placement for chip multiprocessor. CODES+ISSS Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen
2011	C	`conf`	Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip. DDECS Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen
2011	—	`conf`	Process scheduling for future multicore processors. INA-OCMC@HiPEAC Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen
2011	—	`conf`	Study of Hierarchical N-Body Methods for Network-on-Chip Architectures. Euro-Par Workshops (2) Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen
2010	—	`conf`	A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore Processors. Euro-Par Workshops (1) Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen
2010	—	`conf`	Operating System Processor Scheduler Design for Future Chip Multiprocessor. ARCS Workshops Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen
2010	C	`conf`	Tree-model based mapping for energy-efficient and low-latency Network-on-Chip. DDECS Bo Yang, Thomas Canhao Xu, Tero Säntti, Juha Plosila
2009	C	`conf`	Explorations of Honeycomb Topologies for Network-on-Chip. NPC Alexander Wei Yin, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen