Thomas Bourgeat

44 papers A* 18A 2B 2Misc 1Journal 15Unranked 5

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Compass: Navigating the Design Space of Taint Schemes for RTL Security Verification. ASPLOS (2) Yuheng Yang, Qinhan Tan, Thomas Bourgeat, Sharad Malik, Mengjia Yan
2026	—	`conf`	Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits. ASPLOS (2) Yann Herklotz, Ayatallah Elakhras, Martina Camaioni, Paolo Ienne, Lana Josipovic, Thomas Bourgeat
2026	J	`jnl`	RoboPrec: Enabling Reliable Embedded Computing for Robotics by Providing Accuracy Guarantees Across Mixed-Precision Datatypes. IEEE Robotics Autom. Lett. Alp Eren Yilmaz, Thomas Bourgeat, Lillian Pentecost, Brian Plancher, Sabrina M. Neuman
2026	B	`conf`	Towards Composable Proofs of Cache Coherence Protocols. CPP Martina Camaioni, Yann Herklotz, Tz-Ching Yu, Thomas Bourgeat
2025	J	`jnl`	Automatic ISA analysis for Secure Context Switching. CoRR Neelu S. Kalani, Thomas Bourgeat, Guerney D. H. Hunt, Wojciech Ozga
2025	J	`jnl`	CaSA: End-to-End Quantitative Security Analysis of Randomly Mapped Caches. IEEE Des. Test Thomas Bourgeat, Jules Drean, Yuheng Yang, Lillian Tsai, Joel S. Emer, Mengjia Yan
2025	A*	`conf`	Fast End-to-End Performance Simulation of Accelerated Hardware-Software Stacks. SOSP Jiacheng Ma, Jonas Kaufmann, Emilien Guandalino, Rishabh R. Iyer, Thomas Bourgeat, George Candea
2025	A	`conf`	Interoperability of Proof Systems with SC-TPTP. CADE Simon Guilloud, Julie Cailler, Sankalp Gambhir, Auguste Poiroux, Yann Herklotz, Thomas Bourgeat, Viktor Kuncak
2025	A	`conf`	Lightweight Hypervisor Verification: Putting the Hardware Burger on a Diet. HotOS Charly Castes, François Costa, Nate Foster, Thomas Bourgeat, Edouard Bugnion
2025	J	`jnl`	Making Concurrent Hardware Verification Sequential. PLDI Thomas Bourgeat, Jiazheng Liu, Adam Chlipala, Arvind
2025	—	`conf`	Parendi: Thousand-Way Parallel RTL Simulation. ASPLOS (2) Mahyar Emami, Thomas Bourgeat, James R. Larus
2025	—	`conf`	RTL Verification for Secure Speculation Using Contract Shadow Logic. ASPLOS (1) Qinhan Tan, Yuheng Yang, Thomas Bourgeat, Sharad Malik, Mengjia Yan
2025	A*	`conf`	Save what must be saved: Secure context switching with Sailor. USENIX Security Symposium Neelu S. Kalani, Thomas Bourgeat, Guerney D. H. Hunt, Wojciech Ozga
2025	J	`jnl`	SystolicAttention: Fusing FlashAttention within a Single Systolic Array. CoRR Jiawei Lin, Guokai Chen, Yuanlong Li, Thomas Bourgeat
2025	A*	`conf`	The Design and Implementation of a Virtual Firmware Monitor. SOSP Charly Castes, François Costa, Neelu S. Kalani, Timothy Roscoe, Nate Foster, Thomas Bourgeat, Edouard Bugnion
2025	A*	`conf`	eBPF Misbehavior Detection: Fuzzing with a Specification-Based Oracle. SOSP Tao Lyu, Kumar Kartikeya Dwivedi, Thomas Bourgeat, Mathias Payer, Meng Xu, Sanidhya Kashyap
2024	J	`jnl`	Formal Verification for Secure Processors: A Guide for Computer Architects. Computer Mengjia Yan, Thomas Bourgeat, Sharad Malik
2024	J	`jnl`	Parendi: Thousand-Way Parallel RTL Simulation. CoRR Mahyar Emami, Thomas Bourgeat, James R. Larus
2024	A*	`conf`	Performance Interfaces for Hardware Accelerators. OSDI Jiacheng Ma, Rishabh R. Iyer, Sahand Kashani, Mahyar Emami, Thomas Bourgeat, George Candea
2024	J	`jnl`	RTL Verification for Secure Speculation Using Contract Shadow Logic. CoRR Qinhan Tan, Yuheng Yang, Thomas Bourgeat, Sharad Malik, Mengjia Yan
2024	A*	`conf`	Specification and Verification of Strong Timing Isolation of Hardware Enclaves. CCS Stella Lau, Thomas Bourgeat, Clément Pit-Claudel, Adam Chlipala
2024	B	`conf`	Verifying Software Emulation of an Unsupported Hardware Instruction. ITP Samuel Gruetter, Thomas Bourgeat, Adam Chlipala
2023	J	`jnl`	Citadel: Side-Channel-Resistant Enclaves with Secure Shared Memory on a Speculative Out-of-Order Processor. CoRR Jules Drean, Miguel Gomez-Garcia, Thomas Bourgeat, Srinivas Devadas
2023	J	`jnl`	Flexible Instruction-Set Semantics via Abstract Monads (Experience Report). Proc. ACM Program. Lang. Thomas Bourgeat, Ian Clester, Andres Erbsen, Samuel Gruetter, Pratap Singh, Andy Wright, Adam Chlipala
2023	A*	`conf`	Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes. ISCA Peter W. Deutsch, Weon Taek Na, Thomas Bourgeat, Joel S. Emer, Mengjia Yan
2023	A*	`conf`	Pensieve: Microarchitectural Modeling for Security Evaluation. ISCA Yuheng Yang, Thomas Bourgeat, Stella Lau, Mengjia Yan
2023	A*	`conf`	RoboShape: Using Topology Patterns to Scalably and Flexibly Deploy Accelerators Across Robots. ISCA Sabrina M. Neuman, Radhika Ghosal, Thomas Bourgeat, Brian Plancher, Vijay Janapa Reddi
2023	—	`—`	Specification and verification of sequential machines in rule-based hardware languages Thomas Bourgeat
2022	A*	`conf`	DAGguise: mitigating memory timing side channels. ASPLOS Peter W. Deutsch, Yuheng Yang, Thomas Bourgeat, Jules Drean, Joel S. Emer, Mengjia Yan
2021	J	`jnl`	A Multipurpose Formal RISC-V Specification. CoRR Thomas Bourgeat, Ian Clester, Andres Erbsen, Samuel Gruetter, Andrew Wright, Adam Chlipala
2021	J	`jnl`	Accelerating Robot Dynamics Gradients on a CPU, GPU, and FPGA. IEEE Robotics Autom. Lett. Brian Plancher, Sabrina M. Neuman, Thomas Bourgeat, Scott Kuindersma, Srinivas Devadas, Vijay Janapa Reddi
2021	A*	`conf`	Effective simulation and debugging for a high-level hardware language using software compilers. ASPLOS Clément Pit-Claudel, Thomas Bourgeat, Stella Lau, Arvind, Adam Chlipala
2021	A*	`conf`	FlexMiner: A Pattern-Aware Accelerator for Graph Pattern Mining. ISCA Xuhao Chen, Tianhao Huang, Shuotao Xu, Thomas Bourgeat, Chanwoo Chung, Arvind
2021	A*	`conf`	Robomorphic computing: a design methodology for domain-specific accelerators parameterized by robot morphology. ASPLOS Sabrina M. Neuman, Brian Plancher, Thomas Bourgeat, Thierry Tambe, Srinivas Devadas, Vijay Janapa Reddi
2020	A*	`conf`	AQUOMAN: An Analytic-Query Offloading Machine. MICRO Shuotao Xu, Thomas Bourgeat, Tianhao Huang, Hojun Kim, Sungjin Lee, Arvind
2020	A*	`conf`	CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches. MICRO Thomas Bourgeat, Jules Drean, Yuheng Yang, Lillian Tsai, Joel S. Emer, Mengjia Yan
2020	A*	`conf`	The essence of Bluespec: a core language for rule-based hardware design. PLDI Thomas Bourgeat, Clément Pit-Claudel, Adam Chlipala, Arvind
2019	J	`jnl`	Composable Building Blocks to Open Up Processor Design. IEEE Micro Sizhuo Zhang, Andrew Wright, Thomas Bourgeat
2019	A*	`conf`	MI6: Secure Enclaves in a Speculative Out-of-Order Processor. MICRO Thomas Bourgeat, Ilia A. Lebedev, Andrew Wright, Sizhuo Zhang, Arvind, Srinivas Devadas
2018	A*	`conf`	Composable Building Blocks to Open up Processor Design. MICRO Sizhuo Zhang, Andrew Wright, Thomas Bourgeat, Arvind
2018	J	`jnl`	MI6: Secure Enclaves in a Speculative Out-of-Order Processor. CoRR Thomas Bourgeat, Ilia A. Lebedev, Andrew Wright, Sizhuo Zhang, Arvind, Srinivas Devadas
2016	—	`conf`	Specification Mining for Asynchronous Controllers. ASYNC Javier de San Pedro, Thomas Bourgeat, Jordi Cortadella
2014	Misc	`conf`	New Algorithmic Approaches to Point Constellation Recognition. SEC Thomas Bourgeat, Julien Bringer, Hervé Chabanne, Robin Champenois, Jérémie Clément, Houda Ferradi, Marc Heinrich, Paul Melotti, David Naccache, Antoine Voizard
2014	J	`jnl`	New Algorithmic Approaches to Point Constellation Recognition. CoRR Thomas Bourgeat, Julien Bringer, Hervé Chabanne, Robin Champenois, Jérémie Clément, Houda Ferradi, Marc Heinrich, Paul Melotti, David Naccache, Antoine Voizard