Thomas B. Preußer

55 papers A 1B 11C 4Misc 1Journal 23Unranked 14

Year	Rank	Type	Title / Venue / Authors
2025	B	`conf`	FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMS. FPL Shashwat Khandelwal, Jakoba Petri-Koenig, Thomas B. Preußer, Michaela Blott, Shanker Shreejith
2025	J	`jnl`	FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMs. CoRR Shashwat Khandelwal, Jakoba Petri-Koenig, Thomas B. Preußer, Michaela Blott, Shreejith Shanker
2025	J	`jnl`	Parallel Accurate Minifloat MACCs for Neural Network Inference on Versal FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hans Jakob Damsgaard, Konstantin Hoßfeld, Jari Nurmi, Thomas B. Preußer
2025	J	`jnl`	SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators. CoRR Yaman Umuroglu, Christoph Berganski, Felix Jentzsch, Michal Danilowicz, Tomasz Kryjak, Charalampos Bezaitis, Magnus Själander, Ian Colbert, Thomas B. Preußer, Jakoba Petri-Koenig, Michaela Blott
2024	J	`jnl`	High-efficiency Compressor Trees for Latest AMD FPGAs. ACM Trans. Reconfigurable Technol. Syst. Konstantin Hoßfeld, Hans Jakob Damsgaard, Jari Nurmi, Michaela Blott, Thomas B. Preußer
2024	B	`conf`	Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs. FPL Shivam Aggarwal, Hans Jakob Damsgaard, Alessandro Pappalardo, Giuseppe Franco, Thomas B. Preußer, Michaela Blott, Tulika Mitra
2023	J	`jnl`	AMNES: Accelerating the computation of data correlation using FPGAs. Proc. VLDB Endow. Monica Chiosa, Thomas B. Preußer, Michaela Blott, Gustavo Alonso
2023	J	`jnl`	On the RTL Implementation of FINN Matrix Vector Unit. ACM Trans. Embed. Comput. Syst. Syed Asad Alam, David Gregg, Giulio Gambardella, Thomas B. Preußer, Michaela Blott
2023	J	`jnl`	Post-Training Quantization with Low-precision Minifloats and Integers on FPGAs. CoRR Shivam Aggarwal, Alessandro Pappalardo, Hans Jakob Damsgaard, Giuseppe Franco, Thomas B. Preußer, Michaela Blott, Tulika Mitra
2022	J	`jnl`	Everything You Always Wanted to Know About Embedded Trace. Computer Thomas B. Preußer, Smitha Gautham, Abhi D. Rajagopala, Carl R. Elks, Alexander Weiss
2021	—	`conf`	MicroRec: Efficient Recommendation Inference by Hardware and Data Structure Solutions. MLSys Wenqi Jiang, Zhenhao He, Shuai Zhang, Thomas B. Preußer, Kai Zeng, Liang Feng, Jiansong Zhang, Tongxuan Liu, Yong Li, Jingren Zhou, Ce Zhang, Gustavo Alonso
2021	J	`jnl`	Understanding and Fixing Complex Faults in Embedded Cyberphysical Systems. Computer Alexander Weiss, Smitha Gautham, Athira Varma Jayakumar, Carl R. Elks, D. Richard Kuhn, Raghu N. Kacker, Thomas B. Preußer
2021	J	`jnl`	Understanding and Fixing Complex Faults in Embedded Cyberphysical Systems. CoRR Alexander Weiss, Smitha Gautham, Athira Varma Jayakumar, Carl R. Elks, D. Richard Kuhn, Raghu N. Kacker, Thomas B. Preußer
2020	B	`conf`	HyperLogLog Sketch Acceleration on FPGA. FPL Amit Kulkarni, Monica Chiosa, Thomas B. Preußer, Kaan Kara, David Sidler, Gustavo Alonso
2020	J	`jnl`	HyperLogLog Sketch Acceleration on FPGA. CoRR Amit Kulkarni, Monica Chiosa, Thomas B. Preußer, Kaan Kara, David Sidler, Gustavo Alonso
2020	J	`jnl`	MicroRec: Accelerating Deep Recommendation Systems to Microseconds by Hardware and Data Structure Solutions. CoRR Wenqi Jiang, Zhenhao He, Shuai Zhang, Thomas B. Preußer, Kai Zeng, Liang Feng, Jiansong Zhang, Tongxuan Liu, Yong Li, Jingren Zhou, Ce Zhang, Gustavo Alonso
2020	B	`conf`	Using DSP Slices as Content-Addressable Update Queues. FPL Thomas B. Preußer, Monica Chiosa, Alexander Weiss, Gustavo Alonso
2020	J	`jnl`	Using DSP Slices as Content-Addressable Update Queues. CoRR Thomas B. Preußer, Monica Chiosa, Alexander Weiss, Gustavo Alonso
2019	J	`jnl`	An easy counting lemma. Discret. Appl. Math. Matthias R. Engelhardt, Thomas B. Preußer
2019	J	`jnl`	Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing. CoRR Yaman Umuroglu, Davide Conficconi, Lahiru Rasnayake, Thomas B. Preußer, Magnus Själander
2019	J	`jnl`	Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing. ACM Trans. Reconfigurable Technol. Syst. Yaman Umuroglu, Davide Conficconi, Lahiru Rasnayake, Thomas B. Preußer, Magnus Själander
2018	J	`jnl`	FINN- ACM Trans. Reconfigurable Technol. Syst. Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser, Kees A. Vissers
2018	J	`jnl`	FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. CoRR Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu
2018	J	`jnl`	Generic and Universal Parallel Matrix Summation with a Flexible Compression Goal for Xilinx FPGAs. CoRR Thomas B. Preußer
2018	J	`jnl`	Inference of Quantized Neural Networks on Heterogeneous All-Programmable Devices. CoRR Thomas B. Preußer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott
2018	A	`conf`	Inference of quantized neural networks on heterogeneous all-programmable devices. DATE Thomas B. Preußer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott
2018	J	`jnl`	QBM - Mapping User-Specified Functions to Programmable Logic through a QBF Satisfiability Problem. CoRR Thomas B. Preußer
2018	J	`jnl`	Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. CoRR Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser
2017	B	`conf`	Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs. FPL Thomas B. Preußer
2017	C	`conf`	Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC. DDECS Patrick Russell, Jens Döge, Christoph Hoppe, Thomas B. Preußer, Peter Reichel, Peter Schneider
2017	J	`jnl`	Putting Queens in Carry Chains, N o̱27. J. Signal Process. Syst. Thomas B. Preußer, Matthias R. Engelhardt
2017	C	`conf`	Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. ICCD Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser
2016	—	`conf`	Design Kernel Exploration Using QBF-Based Boolean Matching. SiPS Thomas B. Preußer, Fredo Erxleben
2016	—	`conf`	Survey on and re-evaluation of wide adder architectures on FPGAs. ReConFig Thomas B. Preußer, Markus Krause
2016	—	`conf`	The portable open-source IP core and utility library PoC. ReConFig Thomas B. Preußer, Martin Zabel, Patrick Lehmann, Rainer G. Spallek
2015	B	`conf`	An LZ77-style bit-level compression for trace data compaction. FPL Kai-Uwe Irrgang, Thomas B. Preußer
2015	—	`conf`	Kompression von Tracedaten auf Bitebene basierend auf einem LZ77-Wörterbuchansatz. GI-Jahrestagung Kai-Uwe Irrgang, Thomas B. Preußer, Rainer G. Spallek
2014	—	`conf`	PoC-align: An open-source alignment accelerator using FPGAs. ReConFig Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek
2014	B	`conf`	Ready PCIe data streaming solutions for FPGAs. FPL Thomas B. Preußer, Rainer G. Spallek
2013	B	`conf`	Weasel: A platform-independent streaming-optimized SATA controller. FPL Patrick Lehmann, Thomas Frank, Oliver Knodel, Steffen Köhler, Thomas B. Preußer, Rainer G. Spallek
2012	—	`conf`	Increasing the efficiency of an embedded multi-core bytecode processor using an object cache. JTRES Martin Zabel, Thomas B. Preußer, Rainer G. Spallek
2012	Misc	`conf`	Short-Read Mapping by a Systolic Custom FPGA Computation. FCCM Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek
2011	C	`conf`	Accelerating Computations on FPGA Carry Chains by Operand Compaction. IEEE Symposium on Computer Arithmetic Thomas B. Preußer, Martin Zabel, Rainer G. Spallek
2011	B	`conf`	FPGA-Specific Arithmetic Optimizations of Short-Latency Adders. FPL Hong Diep Nguyen, Bogdan Pasca, Thomas B. Preußer
2011	—	`—`	Increasing the Performance and Predictability of the Code Execution on an Embedded Java Platform (Ansätze zur Steigerung der Leistungsfähigkeit und Vorhersagbarkeit der Codeausführung auf einer eingebetteten Java-Plattform). Thomas B. Preußer
2011	—	`conf`	Next-generation massively parallel short-read mapping on FPGAs. ASAP Oliver Knodel, Thomas B. Preußer, Rainer G. Spallek
2010	—	`conf`	An Embedded GC Module with Support for Multiple Mutators and Weak References. ARCS Thomas B. Preußer, Peter Reichel, Rainer G. Spallek
2010	B	`conf`	Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains. FPL Thomas B. Preußer, Rainer G. Spallek
2010	—	`conf`	Solving Sudokus through an incidence matrix on an FPGA. FPT Michael Dittrich, Thomas B. Preußer, Rainer G. Spallek
2010	—	`conf`	The embedded Java benchmark suite JemBench. JTRES Martin Schoeberl, Thomas B. Preußer, Sascha Uhrig
2009	—	`conf`	High-Level Architecture Modelling Assisting the Processor Platform Development, Debugging and Simulation. MBMV Martin Zabel, Thomas B. Preußer, Rainer G. Spallek
2009	B	`conf`	Mapping basic prefix computations to fast carry-chain structures. FPL Thomas B. Preußer, Rainer G. Spallek
2007	C	`conf`	Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. DSD Martin Zabel, Thomas B. Preußer, Peter Reichel, Rainer G. Spallek
2006	—	`conf`	Analysis of a Fully-Scalable Digital Fractional Clock Divider. ASAP Thomas B. Preußer, Rainer G. Spallek
2005	—	`conf`	Design space exploration of coarse-grain reconfigurable DSPs. ReConFig Martin Zabel, Steffen Köhler, Martin Zimmerling, Thomas B. Preußer, Rainer G. Spallek