Thilo Pionteck

132 papers A* 1A 4B 9C 11Misc 2Journal 30Unranked 64

Year	Rank	Type	Title / Venue / Authors
2026	—	`ed.`	Architecture of Computing Systems - 38th International Conference, ARCS 2025, Kiel, Germany, April 22-24, 2025, Proceedings ARCS Sven Tomforde, Christian Krupitzer, Stéphane Vialle, Estela Suarez, Thilo Pionteck
2025	J	`jnl`	Evaluating Rapid Makespan Predictions for Heterogeneous Systems with Programmable Logic. CoRR Martin Wilhelm, Franz Freitag, Max Tzschoppe, Thilo Pionteck
2025	—	`conf`	Static task mapping for heterogeneous systems based on series-parallel decompositions. IPDPS (Workshops) Martin Wilhelm, Thilo Pionteck
2025	J	`jnl`	Static task mapping for heterogeneous systems based on series-parallel decompositions. CoRR Martin Wilhelm, Thilo Pionteck
2024	—	`conf`	An Architectural Template for FPGA Overlays Targeting Data Flow Applications. IPDPS (Workshops) Anna Drewes, Vitalii Burtsev, Bala Gurumurthy, Martin Wilhelm, David Broneske, Gunter Saake, Thilo Pionteck
2024	—	`ed.`	Architecture of Computing Systems - 37th International Conference, ARCS 2024, Potsdam, Germany, May 14-16, 2024, Proceedings ARCS Dietmar Fey, Benno Stabernack, Stefan Lankes, Mathias Pacher, Thilo Pionteck
2024	B	`conf`	Exploring the Versal AI Engines for Signal Processing in Radio Astronomy. FPL Victor Van Wijhe, Vincent Sprave, Daniele Passaretti, Nikolaos Alachiotis, Gerrit Grutzeck, Thilo Pionteck, Steven van der Vlugt
2024	—	`conf`	Impact of Wave Pipelining on NoCs for Heterogeneous Monolithic 3D SoCs. MOCAST Max Tzschoppe, Daniele Passaretti, Amir Najafi, Sebastian Fischer, Martin Wilhelm, Alberto García-Ortiz, Thilo Pionteck
2024	—	`conf`	Large Filter Low-Level Processing by Edge TPU. VISIGRAPP (3): VISAPP Gerald Krell, Thilo Pionteck
2024	—	`conf`	On-the-Fly CT Image Pre-processing on MPSoC-FPGAs. ARCS Daniele Passaretti, Thilo Pionteck
2023	—	`conf`	A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed Tomography. ARC Daniele Passaretti, Thilo Pionteck
2023	Misc	`conf`	A Flexible and Scalable Reconfigurable FPGA Overlay Architecture for Data-Flow Processing. FCCM Anna Drewes, Vitalii Burtsev, Bala Gurumurthy, Martin Wilhelm, David Broneske, Gunter Saake, Thilo Pionteck
2023	J	`jnl`	A comprehensive modeling approach for the task mapping problem in heterogeneous systems with dataflow processing units. Concurr. Comput. Pract. Exp. Martin Wilhelm, Hanna Geppert, Anna Drewes, Thilo Pionteck
2023	A*	`conf`	ADAMANT: A Query Executor with Plug-In Interfaces for Easy Co-processor Integration. ICDE Bala Gurumurthy, David Broneske, Gabriel Campero Durand, Thilo Pionteck, Gunter Saake
2023	—	`ed.`	Architecture of Computing Systems - 36th International Conference, ARCS 2023, Athens, Greece, June 13-15, 2023, Proceedings ARCS Georgios I. Goumas, Sven Tomforde, Jürgen Brehm, Stefan Wildermann, Thilo Pionteck
2023	J	`jnl`	Enabling Plug-and-Play in Cyber-Physical Systems Using MPSoC-FPGAs. IEEE Access Daniele Passaretti, Max Steiger, Thilo Pionteck
2023	—	`conf`	FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query Processing. ARC Vitalii Burtsev, Martin Wilhelm, Anna Drewes, Bala Gurumurthy, David Broneske, Thilo Pionteck, Gunter Saake
2023	J	`jnl`	Hybrid CPU/GPU/APU accelerated query, insert, update and erase operations in hash tables with string keys. Knowl. Inf. Syst. Tobias Groth, Sven Groppe, Thilo Pionteck, Franz Valdiek, Martin Koppehel
2023	J	`jnl`	Novel insights on atomic synchronization for sort-based group-by on GPUs. Distributed Parallel Databases Bala Gurumurthy, David Broneske, Martin Schäler, Thilo Pionteck, Gunter Saake
2023	C	`conf`	What Happens When Two Multi-Query Optimization Paradigms Combine? - A Hybrid Shared Sub-Expression (SSE) and Materialized View Reuse (MVR) Study. ADBIS Bala Gurumurthy, Vasudev Raghavendra Bidarkar, David Broneske, Thilo Pionteck, Gunter Saake
2022	—	`conf`	Accelerated Parallel Hybrid GPU/CPU Hash Table Queries with String Keys. DEXA (2) Tobias Groth, Sven Groppe, Thilo Pionteck, Franz Valdiek, Martin Koppehel
2022	—	`ed.`	Architecture of Computing Systems - 35th International Conference, ARCS 2022, Heilbronn, Germany, September 13-15, 2022, Proceedings ARCS Martin Schulz, Carsten Trinitis, Nikela Papadopoulou, Thilo Pionteck
2022	—	`conf`	Hardware Isolation Support for Low-Cost SoC-FPGAs. ARCS Daniele Passaretti, Felix Boehm, Martin Wilhelm, Thilo Pionteck
2022	—	`conf`	Modeling Task Mapping for Data-Intensive Applications in Heterogeneous Systems. Euro-Par Workshops Martin Wilhelm, Hanna Geppert, Anna Drewes, Thilo Pionteck
2022	J	`jnl`	Modeling Task Mapping for Data-intensive Applications in Heterogeneous Systems. CoRR Martin Wilhelm, Hanna Geppert, Anna Drewes, Thilo Pionteck
2022	J	`jnl`	Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs. ACM Trans. Model. Comput. Simul. Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García-Ortiz, Thilo Pionteck
2021	—	`conf`	An Investigation of Atomic Synchronization for Sort-Based Group-By Aggregation on GPUs. ICDE Workshops Bala Gurumurthy, David Broneske, Martin Schäler, Thilo Pionteck, Gunter Saake
2021	—	`ed.`	Architecture of Computing Systems - 34th International Conference, ARCS 2021, Virtual Event, June 7-8, 2021, Proceedings ARCS Christian Hochberger, Lars Bauer, Thilo Pionteck
2021	—	`conf`	Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. ISQED Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna
2021	—	`conf`	Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures. ASP-DAC Jan Moritz Joseph, Lennart Bamberg, Geonhwa Jeong, Ruei-Ting Chien, Rainer Leupers, Alberto García-Ortiz, Tushar Krishna, Thilo Pionteck
2021	Misc	`conf`	Configurable Pipelined Datapath for Data Acquisition in Interventional Computed Tomography. FCCM Daniele Passaretti, Thilo Pionteck
2021	B	`conf`	CuART - a CUDA-based, scalable Radix-Tree lookup and update engine. ICPP Martin Koppehel, Tobias Groth, Sven Groppe, Thilo Pionteck
2021	—	`conf`	Dead-Ends in FPGAs for Database Acceleration. SAMOS Anna Drewes, Martin Koppehel, Thilo Pionteck
2021	J	`jnl`	In-Depth Analysis of OLAP Query Performance on Heterogeneous Hardware. Datenbank-Spektrum David Broneske, Anna Drewes, Bala Gurumurthy, Imad Hajjar, Thilo Pionteck, Gunter Saake
2021	—	`conf`	StreamGrid - An AXI-Stream-Compliant Overlay Architecture. ARC Christopher Blochwitz, León Philipp, Mladen Berekovic, Thilo Pionteck
2020	—	`ed.`	Architecture of Computing Systems - ARCS 2020 - 33rd International Conference, Aachen, Germany, May 25-28, 2020, Proceedings ARCS André Brinkmann, Wolfgang Karl, Stefan Lankes, Sven Tomforde, Thilo Pionteck, Carsten Trinitis
2020	J	`jnl`	Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. CoRR Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna
2020	J	`jnl`	Hardware-aided update acceleration in a hybrid Semantic Web database system. J. Supercomput. Dennis Heinrich, Stefan Werner, Christopher Blochwitz, Thilo Pionteck, Sven Groppe
2020	—	`conf`	Hardware/Software Co-Design of a control and data acquisition system for Computed Tomography. MOCAST Daniele Passaretti, Thilo Pionteck
2020	—	`conf`	He..ro DB: A Concept for Parallel Data Processing on Heterogeneous Hardware. ARCS Michael Müller, Thomas Leich, Thilo Pionteck, Gunter Saake, Jens Teubner, Olaf Spinczyk
2020	—	`conf`	Optimising Operator Sets for Analytical Database Processing on FPGAs. ARC Anna Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck
2020	—	`conf`	Parallelizing Approximate Search on Adaptive Radix Trees. SEBD Tobias Groth, Sven Groppe, Martin Koppehel, Thilo Pionteck
2020	—	`conf`	Ultra-Low-Latency Video Encoding on Heterogenous Hardware Platforms. FPT Martin Koppehel, Thilo Pionteck
2020	—	`conf`	When Vectorwise Meets Hyper, Pipeline Breakers Become the Moderator. ADMS@VLDB Balasubramanian Gurumurthy, Imad Hajjar, David Broneske, Thilo Pionteck, Gunter Saake
2019	—	`ed.`	Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Copenhagen, Denmark, May 20-23, 2019, Proceedings ARCS Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck
2019	—	`conf`	Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips. MOCAST Jan Moritz Joseph, Dominik Ermel, Tobias Drewes, Lennart Bamberg, Alberto García-Ortiz, Thilo Pionteck
2019	J	`jnl`	Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment. Integr. Lennart Bamberg, Jan Moritz Joseph, Thilo Pionteck, Alberto García Ortiz
2019	J	`jnl`	NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures. IEEE Access Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García Ortiz, Thilo Pionteck
2019	J	`jnl`	NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures. CoRR Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García-Ortiz, Thilo Pionteck
2019	J	`jnl`	Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs. CoRR Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García Ortiz, Thilo Pionteck
2019	J	`jnl`	Simulation environment for link energy estimation in networks-on-chip with virtual channels. Integr. Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz
2019	—	`conf`	Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models. FPT Daniele Passaretti, Jan Moritz Joseph, Thilo Pionteck
2019	C	`conf`	System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips. ICCD Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck
2019	J	`jnl`	System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips. CoRR Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck
2018	—	`conf`	Adaptive Data Processing in Heterogeneous Hardware Systems. Grundlagen von Datenbanken Bala Gurumurthy, Tobias Drewes, David Broneske, Gunter Saake, Thilo Pionteck
2018	—	`ed.`	Architecture of Computing Systems - ARCS 2018 - 31st International Conference, Braunschweig, Germany, April 9-12, 2018, Proceedings ARCS Mladen Berekovic, Rainer Buchty, Heiko Hamann, Dirk Koch, Thilo Pionteck
2018	—	`conf`	Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels. PATMOS Lennart Bamberg, Jan Moritz Joseph, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz
2018	J	`jnl`	Cooking DBMS Operations using Granular Primitives - An Overview on a Primitive-based RDBMS Query Evaluation. Datenbank-Spektrum Bala Gurumurthy, David Broneske, Tobias Drewes, Thilo Pionteck, Gunter Saake
2018	—	`conf`	Efficient Inter-Kernel Communication for OpenCL Database Operators on FPGAs. FPT Tobias Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck
2018	—	`conf`	Hardware-Accelerated Index Construction for Semantic Web. FPT Christopher Blochwitz, Julian Wolff, Mladen Berekovic, Dennis Heinrich, Sven Groppe, Jan Moritz Joseph, Thilo Pionteck
2018	J	`jnl`	Integration of FPGAs in Database Management Systems: Challenges and Opportunities. Datenbank-Spektrum Andreas Becher, Lekshmi B. G., David Broneske, Tobias Drewes, Bala Gurumurthy, Klaus Meyer-Wegener, Thilo Pionteck, Gunter Saake, Jürgen Teich, Stefan Wildermann
2018	—	`conf`	Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs. ReCoSoC Jan Moritz Joseph, Lennart Bamberg, Gerald Krell, Imad Hajjar, Alberto García Ortiz, Thilo Pionteck
2017	—	`conf`	An FPGA-based prototyping framework for Networks-on-Chip. ReConFig Tobias Drewes, Jan Moritz Joseph, Thilo Pionteck
2017	—	`ed.`	Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 3-6, 2017, Proceedings ARCS Jens Knoop, Wolfgang Karl, Martin Schulz, Koji Inoue, Thilo Pionteck
2017	J	`jnl`	Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs. Microprocess. Microsystems Jan Moritz Joseph, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck
2017	—	`conf`	Continuous live-tracing as debugging approach on FPGAs. ReConFig Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck
2017	—	`conf`	Design method for asymmetric 3D interconnect architectures with high level models. ReCoSoC Jan Moritz Joseph, Lennart Bamberg, Sven Wrieden, Dominik Ermel, Alberto García Ortiz, Thilo Pionteck
2017	—	`conf`	Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS. ReConFig Jan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker, Thilo Pionteck
2017	—	`conf`	Hardware-Accelerated Radix-Tree Based String Sorting for Big Data Applications. ARCS Christopher Blochwitz, Julian Wolff, Jan Moritz Joseph, Stefan Werner, Dennis Heinrich, Sven Groppe, Thilo Pionteck
2017	J	`jnl`	Semi-static operator graphs for accelerated query execution on FPGAs. Microprocess. Microsystems Stefan Werner, Dennis Heinrich, Thilo Pionteck, Sven Groppe
2016	—	`conf`	A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip. ReCoSoC Jan Moritz Joseph, Sven Wrieden, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck
2016	J	`jnl`	Accelerated join evaluation in Semantic Web databases by using FPGAs. Concurr. Comput. Pract. Exp. Stefan Werner, Dennis Heinrich, Marc Stelzner, Volker Linnemann, Thilo Pionteck, Sven Groppe
2016	—	`conf`	Adaptive allocation of default router paths in Network-on-Chips for latency reduction. HPCS Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck
2016	—	`ed.`	Architecture of Computing Systems - ARCS 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings ARCS Frank Hannig, João M. P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich
2016	J	`jnl`	Constructing Large-Scale Semantic Web Indices for the Six RDF Collation Orders. Open J. Big Data Sven Groppe, Dennis Heinrich, Christopher Blochwitz, Thilo Pionteck
2016	—	`conf`	Hardware-accelerated pose estimation for embedded systems using Vivado HLS. ReConFig Jan Moritz Joseph, Tobias Winker, Kristian Ehlers, Christopher Blochwitz, Thilo Pionteck
2016	J	`jnl`	RAW 2014: Random Number Generators on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck
2016	J	`jnl`	Runtime Adaptive Hybrid Query Engine based on FPGAs. Open J. Databases Stefan Werner, Dennis Heinrich, Sven Groppe, Christopher Blochwitz, Thilo Pionteck
2015	—	`conf`	An architectural template for composing application specific datapaths at runtime. ReConFig Rico Backasch, Gerald Hempel, Christopher Blochwitz, Stefan Werner, Sven Groppe, Thilo Pionteck
2015	—	`conf`	An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases. ReConFig Christopher Blochwitz, Jan Moritz Joseph, Rico Backasch, Thilo Pionteck, Stefan Werner, Dennis Heinrich, Sven Groppe
2015	—	`conf`	Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs. NORCAS Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck, Alberto García Ortiz
2015	—	`conf`	Automated composition and execution of hardware-accelerated operator graphs. ReCoSoC Stefan Werner, Dennis Heinrich, Jannik Piper, Sven Groppe, Rico Backasch, Christopher Blochwitz, Thilo Pionteck
2015	—	`conf`	Hybrid FPGA approach for a B ReCoSoC Dennis Heinrich, Stefan Werner, Marc Stelzner, Christopher Blochwitz, Thilo Pionteck, Sven Groppe
2015	J	`jnl`	PatTrieSort - External String Sorting based on Patricia Tries. Open J. Databases Sven Groppe, Dennis Heinrich, Stefan Werner, Christopher Blochwitz, Thilo Pionteck
2014	—	`conf`	A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling. ISSoC Jan Moritz Joseph, Thilo Pionteck
2014	—	`conf`	Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation. ReConFig Rico Backasch, Gerald Hempel, Stefan Werner, Sven Groppe, Thilo Pionteck
2014	—	`conf`	Influence of Magnetic Fields and X-Radiation on Ring Oscillators in FPGAs. IPDPS Workshops Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck
2014	C	`conf`	Parallel and Pipelined Filter Operator for Hardware-Accelerated Operator Graphs in Semantic Web Databases. CIT Stefan Werner, Dennis Heinrich, Marc Stelzner, Sven Groppe, Rico Backasch, Thilo Pionteck
2013	—	`conf`	Hardware-accelerated join processing in large Semantic Web databases with FPGAs. HPCS Stefan Werner, Sven Groppe, Volker Linnemann, Thilo Pionteck
2013	—	`conf`	Prioritizing semi-static data streams in network-on-chips for runtime reconfigurable systems. HPCS Thilo Pionteck, Christoph Osterloh
2013	—	`conf`	Register allocation for high-level synthesis of hardware accelerators targeting FPGAs. ReCoSoC Gerald Hempel, Jan Hoyer, Thilo Pionteck, Christian Hochberger
2012	—	`conf`	An Approach for Performance Estimation of Hybrid Systems with FPGAs and GPUs as Coprocessors. ARCS Volker Hampel, Thilo Pionteck, Erik Maehle
2012	—	`conf`	MONSUN II: A small and inexpensive AUV for underwater swarms. ROBOTIK Christoph Osterloh, Thilo Pionteck, Erik Maehle
2011	—	`conf`	Linking Formal Description and Simulation of Runtime Reconfigurable Systems. ReConFig Thilo Pionteck, Christoph Osterloh, Carsten Albrecht
2010	—	`conf`	A concept of a trust management architecture to increase the robustness of nano age devices. DSN Workshops Thilo Pionteck, Werner Brockmann
2010	—	`ch.`	DynaCORE - Dynamically Reconfigurable Coprocessor for Network Processors. Dynamically Reconfigurable Systems Carsten Albrecht, Jürgen Foag, Roman Koch, Erik Maehle, Thilo Pionteck
2010	C	`conf`	Optimizing Runtime Reconfiguration Decisions. EUC Thilo Pionteck, Steffen Sammann, Carsten Albrecht
2009	J	`jnl`	A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime. Int. J. Reconfigurable Comput. Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle
2008	J	`jnl`	Adaptive Communication Architectures for Runtime Reconfigurable System-on-Chips. Parallel Process. Lett. Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle
2008	C	`conf`	Design and Simulation of Runtime Reconfigurable Systems. DDECS Thilo Pionteck, Carsten Albrecht, Roman Koch, Torben Brix, Erik Maehle
2008	B	`conf`	Network processors. FPL Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf
2008	B	`conf`	On the design parameters of runtime reconfigurable systems. FPL Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle
2008	C	`conf`	Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform. PDP Carsten Albrecht, Philipp Roß, Roman Koch, Thilo Pionteck, Erik Maehle
2008	—	`conf`	WCET determination tool for embedded systems software. SimuTools Carsten Albrecht, Roman Koch, Thilo Pionteck, Erik Maehle, Michael Werner, Rudolf Fuchsen
2007	C	`conf`	A Lightweight Framework for Runtime Reconfigurable System Prototyping. IEEE International Workshop on Rapid System Prototyping Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle
2007	A	`conf`	Communication Architectures for Dynamically Reconfigurable FPGA Designs. IPDPS Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner, Jürgen Becker
2007	J	`jnl`	Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). it Inf. Technol. Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck
2007	—	`conf`	Teaching Informatics Students the Secrets of Hardware Design. MSE Thilo Pionteck
2006	A	`conf`	A dynamically reconfigurable packet-switched network-on-chip. DATE Thilo Pionteck, Carsten Albrecht, Roman Koch
2006	A	`conf`	An adaptive system-on-chip for network applications. IPDPS Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle
2006	B	`conf`	Applying Partial Reconfiguration to Networks-On-Chips. FPL Thilo Pionteck, Roman Koch, Carsten Albrecht
2006	—	`conf`	Eine Scheduling Heuristik zur Minimierung der Verlustleistung. MBMV Peter Zipf, Volker Hampel, Manfred Glesner, Thilo Pionteck
2005	C	`conf`	On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction. VLSI-SoC Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
2005	—	`conf`	Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten. ARCS Workshops Heiko Hinkelmann, Thilo Pionteck, Oliver Kleine, Manfred Glesner
2005	—	`conf`	Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. SAMOS Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf
2004	B	`conf`	A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals. FPL Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
2004	—	`conf`	Design of a reconfigurable AES encryption/decryption engine for mobile terminals. ISCAS (2) Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
2004	—	`conf`	Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren. ARCS Workshops Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Lukusa D. Kabulepa, Manfred Glesner
2004	A	`conf`	On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs. FPGA Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
2004	—	`conf`	Reconfigurable platforms for ubiquitous computing. Conf. Computing Frontiers Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan
2003	—	`conf`	Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans. VLSI-SoC (Selected Papers) Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner
2003	C	`conf`	Exploring the Capabilities of Reconfigurable Hardware for OFDM-based WLANs. VLSI-SOC Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner
2003	J	`jnl`	On the Rapid Prototyping of Equalizers for OFDM Systems. Des. Autom. Embed. Syst. Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner
2003	—	`conf`	Reconfiguration requirements for high speed wireless communication systems. FPT Thilo Pionteck, Lukusa D. Kabulepa, Clemens Schlachta, Manfred Glesner
2003	C	`conf`	The requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures. IEEE International Workshop on Rapid System Prototyping Thilo Pionteck, A. Garcya, Lukusa D. Kabulepa, Manfred Glesner
2002	B	`conf`	A Framework for Teaching (Re)Configurable Architectures in Student Projects. FPL Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner
2002	C	`conf`	On the Rapid Prototyping of Equalizers for OFDM Systems. IEEE International Workshop on Rapid System Prototyping Thilo Pionteck, N. Toender, Lukusa D. Kabulepa, Manfred Glesner, Tideya Kella
2001	—	`conf`	Adaptive Systems-on-Chip: Architectures, Technologies and Applications. SBCCI Jürgen Becker, Thilo Pionteck, Manfred Glesner
2001	B	`conf`	Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. FPL Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner
2001	—	`conf`	On the numerical accuracy of CORDIC-based frequency offset compensation in burst oriented OFDM systems. ICECS Lukusa D. Kabulepa, Tideya Kella, Thilo Pionteck, Ralf Ludewig, Jürgen Becker, J. Plechinger, Manfred Glesner
2000	—	`conf`	An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing. SBCCI Jürgen Becker, Thilo Pionteck, Manfred Glesner
2000	B	`conf`	DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. FPL Jürgen Becker, Thilo Pionteck, Manfred Glesner