Thian Fatt Tay

11 papers C 4Journal 5Unranked 2
YearRankTypeTitle / Venue / Authors
2017 J jnl
New Algorithm for Signed Integer Comparison in {2
IEEE Trans. Circuits Syst. I Regul. Pap.
Sachin Kumar, Chip-Hong Chang, Thian Fatt Tay
2016 J jnl
A Non-Iterative Multiple Residue Digit Error Detection and Correction Algorithm in RRNS.
IEEE Trans. Computers
Thian Fatt Tay, Chip-Hong Chang
2016 J jnl
Erratum to "Efficient VLSI Implementation of 2
IEEE Trans. Very Large Scale Integr. Syst.
Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low
2015 C conf
A new unified modular adder/subtractor for arbitrary moduli.
ISCAS
Thian Fatt Tay, Chip-Hong Chang
2015 J jnl
Base Transformation With Injective Residue Mapping for Dynamic Range Reduction in RNS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Thian Fatt Tay, Chip-Hong Chang, Leonel Sousa
2014 C conf
A new algorithm for single residue digit error correction in Redundant Residue Number System.
ISCAS
Thian Fatt Tay, Chip-Hong Chang
2014 — conf
New algorithm for signed integer comparison in four-moduli superset {2
APCCAS
Thian Fatt Tay, Chip-Hong Chang
2013 C conf
A signed integer programmable power-of-two scaler for {2
ISCAS
Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
2013 J jnl
Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n}, 2^{n}+1\}}$.
IEEE Trans. Very Large Scale Integr. Syst.
Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low
2012 C conf
A fast and compact circuit for integer square root computation based on Mitchell logarithmic method.
ISCAS
Joshua Yung Lih Low, Ching-Chuen Jong, Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
2012 — conf
A unified {2
APCCAS
Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang