Theodore W. Manikas

34 papers A 1B 4C 1Journal 12Unranked 16
YearRankTypeTitle / Venue / Authors
2025 B conf
European Test Symposium Teams: an Anniversary Snapshot.
ETS
Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025 J jnl
Secure Controller Area Network (CAN) Transceiver With Embedded Authentication Support.
IEEE Trans. Circuits Syst. I Regul. Pap.
Weizhong Chen, Xianshan Wen, Can Hong, Theodore W. Manikas, Mitchell A. Thornton, Ping Gui
2024 — conf
Dual Use Circuitry for Early Failure Warning and Test.
ISQED
Alexander Coyle, Hui Jiang, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal
2023 J jnl
CNN-Assisted Steganography - Integrating Machine Learning with Established Steganographic Techniques.
CoRR
Andrew Havard, Theodore W. Manikas, Eric C. Larson, Mitchell A. Thornton
2023 B conf
Harvesting Wasted Clock Cycles for Efficient Online Testing.
ETS
Eslam Yassien, Yongjia Xu, Hui Jiang, Thach Nguyen, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal
2023 J jnl
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift.
J. Electron. Test.
Hui Jiang, Fanchen Zhang, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas
2021 J jnl
3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations.
IEEE Trans. Emerg. Top. Comput.
Soha Alhelaly, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Ping Gui, Alfred L. Crouch
2021 — conf
Industrial Control System Anomaly Detection Using Convolutional Neural Network Consensus.
CCTA
Aviraj Sinha, Michael A. Taylor, Nathan Srirama, Theodore W. Manikas, Eric C. Larson, Mitchell A. Thornton
2021 A conf
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits.
ITC
Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar
2019 J jnl
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack.
J. Electron. Test.
Yi Sun, Fanchen Zhang, Hui Jiang, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
2019 — conf
Test Architecture for Fine Grained Capture Power Reduction.
ICECS
Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
2017 — conf
Automated Markov-chain based analysis for large state spaces.
SysCon
Kaitlin N. Smith, Michael A. Taylor, Anna A. Carroll, Theodore W. Manikas, Mitchell A. Thornton
2017 — conf
Detecting a trojan die in 3D stacked integrated circuits.
NATW
Soha Alhelaly, Jennifer Dworak, Theodore W. Manikas, Ping Gui, Kundan Nepal, Alfred L. Crouch
2016 — conf
Reliability block diagram extensions for non-parametric probabilistic analysis.
SysCon
Philip C. Davis, Mitchell A. Thornton, Theodore W. Manikas
2016 — conf
Using Existing Reconfigurable Logic in 3D Die Stacks for Test.
NATW
Fanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, Ping Gui, R. Iris Bahar, Al Crouch, John C. Potter
2015 — conf
Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas
2015 J jnl
Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams.
J. Multiple Valued Log. Soft Comput.
Theodore W. Manikas, Mitchell A. Thornton, David Y. Feinstein
2015 J jnl
Repairing a 3-D Die-Stack Using Available Programmable Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar, Theodore W. Manikas, Ping Guikundan
2014 — conf
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas
2014 J jnl
On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems.
IEICE Trans. Inf. Syst.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas
2014 — conf
System Probability Distribution Modeling Using MDDs.
ISMVL
Mitchell A. Thornton, Theodore W. Manikas, Stephen A. Szygenda, Shinobu Nagayama
2013 — conf
Built-in Self-Repair in a 3D die stack using programmable logic.
DFTS
Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
2013 C conf
Embedded and real-time systems classes in traditional and distance education format.
FIE
Mitchell A. Thornton, Theodore W. Manikas, Phillip A. Laplante
2013 — conf
Spectral Response of Ternary Logic Netlists.
ISMVL
Mitchell A. Thornton, Theodore W. Manikas
2012 J jnl
Integrated Circuit Channel Routing using a Pareto-Optimal Genetic Algorithm.
J. Circuits Syst. Comput.
Theodore W. Manikas
2012 — conf
Modeling Medical System Threats with Conditional Probabilities Using Multiple-Valued Logic Decision Diagrams.
ISMVL
Theodore W. Manikas, David Y. Feinstein, Mitchell A. Thornton
2011 — conf
Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities.
ISMVL
Theodore W. Manikas, Mitchell A. Thornton, David Y. Feinstein
2010 J jnl
An Electrical Engineering Summer Academy for Middle School and High School Students.
IEEE Trans. Educ.
Peter G. LoPresti, Theodore W. Manikas, Jeff Kohlbeck
2010 J jnl
On-chip thermal optimisation by whitespace reallocation using a constrained particleswarm optimisation algorithm.
IET Circuits Devices Syst.
Debarshi Chatterjee, Theodore W. Manikas
2009 J jnl
A Genetic Algorithm for Autonomous Navigation Using Variable-Monotone Paths.
Int. J. Robotics Autom.
Kamran H. Sedighi, Theodore W. Manikas, Kaveh Ashenayi, Roger L. Wainwright
2008 — conf
Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells.
ISMVL
Theodore W. Manikas, Dale Teeters
2006 B conf
Evolving A Diverse Collection of Robot Path Planning Problems.
IEEE Congress on Evolutionary Computation
Daniel A. Ashlock, Theodore W. Manikas, Kaveh Ashenayi
2004 B conf
Autonomous local path planning for a mobile robot using a genetic algorithm.
IEEE Congress on Evolutionary Computation
Kamran H. Sedighi, Kaveh Ashenayi, Theodore W. Manikas, Roger L. Wainwright, Heng-Ming Tai
2002 — conf
Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement.
IWLS
Theodore W. Manikas, Gerald R. Kane