Theo J. Powell

12 papers A 8Misc 4
YearRankTypeTitle / Venue / Authors
2006 Misc conf
Reducing Design Verification Cycle Time through Testbench Redundancy.
VLSI Design
Aman Kokrady, Theo J. Powell, S. Ramakrishnan
2005 A conf
Chasing subtle embedded RAM defects for nanometer technologies.
ITC
Theo J. Powell, Amrendra Kumar, Joseph Rayhawk, Nilanjan Mukherjee
2003 A conf
BIST for Deep Submicron ASIC Memories with High Performance Application.
ITC
Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai
2000 Misc conf
Delta Iddq for Testing Reliability.
VTS
Theo J. Powell, James R. Pair, Melissa St. John, Doug Counce
1997 A conf
A 256Meg SDRAM BIST for Disturb Test Application.
ITC
Theo J. Powell, Dan Cline, Francis Hii
1996 Misc conf
Consistently dominant fault model for tristate buffer nets.
VTS
Theo J. Powell
1996 A conf
Correlating Defects to Functional and I
ITC
Theo J. Powell, James R. Pair, Bernard G. Carbajal III
1995 A conf
Test Generation and Design for Test for a Large Multiprocessing DSP.
ITC
Graham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell
1994 Misc conf
Correlating defect level to final test fault coverage for modular structured designs [microcontroller family].
VTS
Theo J. Powell, Kenneth M. Butler, Mike Ales, Roy Haley, Mark Perry
1988 A conf
Testability Features in the TMS370 Family of Microcomputers.
ITC
Theo J. Powell, Fred Hwang, Bill Johnson
1982 A conf
An Architecture for Testable VLSI Processors.
ITC
Satish M. Thatte, D. S. Ho, H.-T. Yuan, Thirumalai Sridhar, Theo J. Powell
1982 A conf
Analysis and Simulation of Parallel Signature Analyzers.
ITC
Thirumalai Sridhar, D. S. Ho, Theo J. Powell, Satish M. Thatte