Themistoklis Haniotakis

47 papers A 1B 1C 3Journal 16Unranked 26
YearRankTypeTitle / Venue / Authors
2024 J jnl
Design of a Reformed Array Logic Binary Multiplier for High-Speed Computations.
CoRR
Sakib Mohammad, Themistoklis Haniotakis
2020 — conf
A Built In Test circuit for waveform classification at high frequencies.
NATW
Konstantinos Poulos, Themistoklis Haniotakis
2020 C conf
ARIAN: A Scalable Method for Adding aRbItrAry Numbers on Modern Processors.
ISCAS
Konstantinos Poulos, Iraklis Anagnostopoulos, Themistoklis Haniotakis
2019 J jnl
Implementation Guidelines of WDSRAM and Comparison with Typical SRAM Using Nanoscale Hierarchical Implementation Model.
J. Circuits Syst. Comput.
Theodoros Simopoulos, George Alexiou, Themistoklis Haniotakis
2019 J jnl
Power efficient synchronous counter design.
Comput. Electr. Eng.
Raghava Katreepalli, Themistoklis Haniotakis
2018 — conf
A 1Kx32 bit WDSRAM page with rapid write access.
DTIS
Theodoros Simopoulos, Themistoklis Haniotakis, George Alexiou
2018 J jnl
A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions.
IEEE Trans. Circuits Syst. I Regul. Pap.
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
2017 A conf
A new method to identify threshold logic functions.
DATE
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
2017 — conf
An enhanced approach to reduce test application time through limited shift operations in scan chains.
NATW
Konstantinos Poulos, Jayasurya Kuchi, Themistoklis Haniotakis
2017 J jnl
Delay Analysis for Current Mode Threshold Logic Gate Designs.
IEEE Trans. Very Large Scale Integr. Syst.
Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas
2017 — conf
High Speed Power Efficient Carry Select Adder Design.
ISVLSI
Raghava Katreepalli, Themistoklis Haniotakis
2017 J jnl
More Efficient Testing of Metal-Oxide Memristor-Based Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
2017 C conf
Reducing power, area, and delay of threshold logic gates considering non-integer weights.
ISCAS
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
2016 J jnl
ATPG for Delay Defects in Current Mode Threshold Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis
2016 — conf
Identification of delay defects on embedded paths using one current sensor.
DTIS
Wisam Aljubouri, Spyros Tragoudas, Themistoklis Haniotakis
2016 — conf
Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design.
ISVLSI
Raghava Katreepalli, Hemanth Chemanchula, Themistoklis Haniotakis, Yiorgos Tsiatouhas
2015 J jnl
A current monitoring technique for I
Integr.
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
2015 — conf
Fast march tests for defects in resistive memory.
NANOARCH
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
2014 — conf
ATPG for transition faults of pipelined threshold logic circuits.
DTIS
Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis
2014 — conf
Diagnosis of segment delay defects with current sensing.
DFT
Wisam Aljubouri, Ahish Mysore Somashekar, Themistoklis Haniotakis, Spyros Tragoudas
2014 — conf
Implementation of a Low Leakage Standard Cell Library based on materials from UMC 65nm technology.
Panhellenic Conference on Informatics
Theodoros Simopoulos, Themistoklis Haniotakis, George Alexiou
2013 — conf
Low power and high speed current-mode memristor-based TLGs.
DFTS
Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas
2012 — conf
Delay Analysis for an N-Input Current Mode Threshold Logic Gate.
ISVLSI
Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas
2012 J jnl
Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission.
Ad Hoc Networks
Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas
2011 — conf
A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate.
DFT
Chandra Babu Dara, Spyros Tragoudas, Themistoklis Haniotakis
2010 J jnl
A Data Capturing Method for Buses on Chip.
IEEE Trans. Circuits Syst. I Regul. Pap.
Michael N. Skoufis, Kedar Karmarkar, Spyros Tragoudas, Themistoklis Haniotakis
2010 — conf
Memory-Less Pipeline Dynamic Circuit Design Technique.
ISVLSI
Themistoklis Haniotakis, Zaher Owda, Yiorgos Tsiatouhas
2008 J jnl
A Current Mode, Parallel, Two-Rail Code Checker.
IEEE Trans. Computers
Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
2008 — conf
A High-Performance Bus Architecture for Strongly Coupled Interconnects.
ISQED
Michael N. Skoufis, Kedar Karmarkar, Themistoklis Haniotakis, Spyros Tragoudas
2007 J jnl
A Methodology for Transistor-Efficient Supergate Design.
IEEE Trans. Very Large Scale Integr. Syst.
Dimitrios Kagaris, Themistoklis Haniotakis
2007 — conf
Glitch Control with Dynamic Receiver Threshold Adjustment.
ISQED
Michael N. Skoufis, Haibo Wang, Themistoklis Haniotakis, Spyros Tragoudas
2007 J jnl
Testable Designs of Multiple Precharged Domino Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
2007 — conf
Transistor-Level Synthesis for Low-Power Applications.
ISQED
Dimitri Kagaris, Themistoklis Haniotakis
2006 J jnl
A Design Technique for Energy Reduction in NORA CMOS Logic.
IEEE Trans. Circuits Syst. I Regul. Pap.
Konstantinos Limniotis, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
2006 — conf
A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism.
ICECS
Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
2006 — conf
An Improved Method for Identifying Linear Dependencies in Path Delay Faults.
ISQED
Edward Flanigan, Themistoklis Haniotakis, Spyros Tragoudas
2006 — conf
Transistor-Level Optimization of Supergates.
ISQED
Dimitri Kagaris, Themistoklis Haniotakis
2005 B conf
A security protocol for sensor networks.
GLOBECOM
Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas
2005 — conf
An embedded IDDQ testing circuit and technique.
ICECS
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
2005 — conf
Design and Evaluation of a Security Scheme for Sensor Networks.
ISQED
Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas
2005 C conf
Fast, Parallel Two-Rail Code Checker with Enhanced Testability.
IOLTS
Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou
2005 — conf
Reduced Test Application Time Based on Reachability Analysis.
ISQED
Themistoklis Haniotakis, Spyros Tragoudas, G. Pani
2004 J jnl
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs.
J. Electron. Test.
Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
2004 J jnl
A unified framework for generating all propagation functions for logic errors and events.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Maria K. Michael, Themistoklis Haniotakis, Spyros Tragoudas
2004 — conf
Security enhancement through multiple path transmission in ad hoc networks.
ICC
Themistoklis Haniotakis, Spyros Tragoudas, Constantinos Kalapodas
2003 — conf
A low power NORA circuit design technique based on charge recycling.
ICECS
Yiorgos Tsiatouhas, Konstantinos Limniotis, Angela Arapoyanni, Themistoklis Haniotakis
2002 — conf
SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology.
ISCAS (5)
A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis