Tezaswi Raja

13 papers B 1Misc 4Journal 3Unranked 5
YearRankTypeTitle / Venue / Authors
2024 — conf
A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode.
CICC
Siddharth Saxena, Sudhir S. Kudva, Vijay Srinivasan, Miguel Rodriguez, Walter Li, Shalimar Rasheed, Gaurav Ajwani, Tezaswi Raja, Santosh A, C. Thomas Gray
2019 — conf
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.
ASYNC
Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany
2015 J jnl
An Energy-Recovering Reconfigurable Series Resonant Clocking Scheme for Wide Frequency Operation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ignatius Bezzam, Chakravarthy Mathiazhagan, Tezaswi Raja, Shoba Krishnan
2013 — conf
Low power low voltage wide frequency resonant clock and data circuits for power reductions.
LASCAS
Ignatius Bezzam, Shoba Krishnan, Tezaswi Raja, Chakravarthy Mathiazhagan
2010 — conf
Digital Logic Implementation in Memristor-Based Crossbars - A Tutorial.
DELTA
Tezaswi Raja, Samiha Mourad
2009 J jnl
Variable Input Delay CMOS Logic for Low Power Design.
IEEE Trans. Very Large Scale Integr. Syst.
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2006 J jnl
Transistor Sizing of Logic Gates to Maximize Input Delay Variability.
J. Low Power Electron.
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2005 — conf
Design of Variable Input Delay Gates for Low Dynamic Power Circuits.
PATMOS
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2005 Misc conf
Variable Input Delay CMOS Logic for Low Power Design.
VLSI Design
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2004 Misc conf
A Tuturial on the Emerging Nanotechnology Devices.
VLSI Design
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2004 Misc conf
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed.
VLSI Design
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
2004 B conf
Using a Jini based desktop Grid for test vector compaction and a refined economic model.
CCGRID
Tezaswi Raja, Manish Parashar
2003 Misc conf
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program.
VLSI Design
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell