Tetsuya Matsumura

27 papers C 3Misc 1Journal 8Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	Misc	`conf`	20-µs Low-latency Simple Video Coding with High Compression Ratio for IoT Video-transmission. ICNC Mai Yamakawa, Seiji Mochizuki, Yu Kuwahara, Tsuyoshi Kato, Kousuke Imamura, Tetsuya Matsumura
2023	—	`conf`	CGTI-Net: Deep-Learning-Based Object Detection Network for High-Resolution Aerial Images. IoTaIS Yusei Horikawa, Seiji Mochizuki, Kousuke Imamura, Tetsuya Matsumura
2023	—	`conf`	Clustering Re-Inference Algorithm for Deep Learning-Based Hierarchical Object Detection System. GCCE Yusei Horikawa, Renpei Yoshida, Seiji Mochizuki, Tetsuya Matsumura
2023	—	`conf`	Ultra-Low-Latency Video Coding with Reduced Frame Memory Structure for 4K/8K High-Resolution Video. GCCE Mai Yamaguchi, Mai Yamakawa, Seiji Mochizuki, Kousuke Imamura, Toshiki Kanamoto, Tetsuya Matsumura
2022	—	`conf`	Implementation of Deep Learning-based Hierarchical Object Detection System for High-Resolution Images. GCCE Makoto Sugaya, Yusei Horikawa, Kazuma Mashiko, Tomoya Minagawa, Tetsuya Matsumura
2019	—	`conf`	Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis. ISPACS Kosuke Fukava, Kaito Mori, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura, Seiji Mochizuki
2019	J	`jnl`	Reconfigurable 3D Sound Processor and Its Automatic Design Environment Using High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura
2019	—	`conf`	Scalable Architecture for High-Resolution Real-time Optical Flow Processor. IoTaIS Kousuke Imamura, Satoshi Kanda, Saya Ohira, Yoshio Matsuda, Tetsuya Matsumura
2018	—	`conf`	Automatic Design Environment using High-level Synthesis for Reconfigurable 3D Sound Processor. ISPACS Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura
2018	—	`conf`	Ultra-low-latency Video Coding Method for Autonomous Vehicles and Virtual Reality Devices. IOTAIS Seiji Mochizuki, Kousuke Imamura, Kaito Mori, Yoshio Matsuda, Tetsuya Matsumura
2017	J	`jnl`	A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kousuke Imamura, Ryota Honda, Yoshifumi Kawamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Tetsuya Matsumura, Yoshio Matsuda
2017	J	`jnl`	Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yu Suzuki, Masato Ito, Satoshi Kanda, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura
2017	C	`conf`	Design for three-dimensional sound processor using high-level synthesis. DDECS Saya Ohira, Tetsuya Matsumura
2016	J	`jnl`	A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda, Tetsuya Matsumura, Hiroshi Makino, Kazutami Arimoto
2016	—	`conf`	Automatic rule registration and deletion function on a packet lookup engine LSI. ISPACS Tetsuya Matsumura, Kousuke Imamura, Yoshifumi Kawamura, Yoshio Matsuda
2015	C	`conf`	A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm. DDECS Tetsuya Matsumura, Aoi Kurokawa, Kousuke Imamura, Yoshio Matsuda
2015	J	`jnl`	Human-centered X-Y-T-space path planning for mobile robot in dynamic environments. Robotics Auton. Syst. Ippei Nishitani, Tetsuya Matsumura, Mayumi Ozawa, Ayanori Yorozu, Masaki Takahashi
2014	J	`jnl`	28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. IEEE Trans. Very Large Scale Integr. Syst. Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa
2014	C	`conf`	The LSI implementation of a memory based field programmable device for MCU peripherals. DDECS Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda
2013	—	`conf`	A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. ISQED Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda
2012	—	`conf`	Simultaneous Control of Translational and Rotational Motion for Autonomous Omnidirectional Mobile Robot - 2nd Report: Robot Model Considering Moving Parts and Evaluation of Movable Area by Heights. ICINCO (2) Ayanori Yorozu, Takafumi Suzuki, Tetsuya Matsumura, Masaki Takahashi
2012	—	`conf`	Simultaneous Control of Translational and Rotational Motion for Autonomous Omnidirectional Mobile Robot Considering Shape of the Robot and Movable Area by Heights. IAS (1) Ayanori Yorozu, Takafumi Suzuki, Tetsuya Matsumura, Masaki Takahashi
2011	—	`conf`	Obstacle Avoidance with Simultaneous Translational and Rotational Motion Control for Autonomous Mobile Robot. ICINCO (2) Masaki Takahashi, Takafumi Suzuki, Tetsuya Matsumura, Ayanori Yorozu
2002	J	`jnl`	A 99-mm IEEE J. Solid State Circuits Satoshi Kumaki, Hidehiro Takata, Yoshihide Ajioka, Tsukasa Ooishi, Kazuya Ishihara, Atsuo Hanami, Takaharu Tsuji, Tetsuya Watanabe, Chikayoshi Morishima, Tomoaki Yoshizawa, Hidenori Sato, Shin-ichi Hattori, Atsushi Koshio, Kazuhiro Tsukamoto, Tetsuya Matsumura
1999	—	`conf`	A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores. CICC Satoshi Kumaki, Tetsuya Matsumura, Kamya Ishihara, Hiroshi Segawa, Kiyofumi Kawamoto, Hideo Ohira, Toshiaki Shimada, Hidenori Sato, Takashi Hattori, Tetsuro Wada, Hiroshi Honma, Tetsuya Watanabe, Hisakazu Sato, Ken'ichi Asano, Toyohiko Yoshida
1998	—	`conf`	A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications. CICC Atsuo Hanami, Stefan Scotzniovsky, Kazuya Ishihara, Tetsuya Matsumura, Shin'ichi Takeuchi, Haruyuki Ohkuma, Koji Nishigaki, Hirokazu Suzuki, Masahiro Kazayama, Toyohiko Yoshida, Koji Tsuchihashi
1990	J	`jnl`	A 24-b 50-ns digital image signal processor. IEEE J. Solid State Circuits Shin-ichi Nakagawa, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shuichi Kato, Masahiro Hatanaka, Hideo Ohira, Yoshiaki Kato, Mamoru Iwatsuki, Kinya Tabuchi, Yasutaka Horiba