Tetsuya Iizuka

141 papers A 3B 3C 9Journal 65Unranked 61

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A 157fsrms-Jitter, -73dBc-Fractional-Spur, Calibration-Free Cascaded SPLL Employing Robust Feedforward Noise Cancellation and MMD-Based Quantization-Error Cancellation with a 60MHz Reference. ISSCC Haoming Zhang, Yongjun He, Yuyang Zhu, Huanyu Ren, Tetsuya Iizuka
2026	J	`jnl`	A 91.8-dB SNDR 24-kHz BW Discrete-Time ΔΣ ADC Employing Gain-Switched FIA With Sampling Noise Cancellation. IEEE Trans. Circuits Syst. II Express Briefs Ximing Wang, Yuyang Zhu, Haoming Zhang, Yunjie Chen, Jiaao Yu, Sota Kano, Ritaro Takenaka, Shuowei Li, Tomohiro Nezuka, Yoshikazu Furuta, Tetsuya Iizuka
2026	J	`jnl`	An 11.95-ENOB 560-MS/s Amplifier-Switching Subranging Analog-to-Digital Converter With Multi-Threshold Comparators. IEEE J. Solid State Circuits Ritaro Takenaka, Tetsuya Iizuka
2025	C	`conf`	A 172.1dB-FoM 19.5kHz-BW DT ΔΣ ADC Using CLS-Assisted Fast Self-Quenching Floating Inverter Amplifier with Sampling Noise Cancellation. ISCAS Ximing Wang, Yo Kumano, Tomohiro Nezuka, Yoshikazu Furuta, Tetsuya Iizuka
2025	—	`conf`	A 96fsrms-Jitter, -70.6dBc-Fractional-Spur Cascaded PLL Employing Two MMDs with Shared DSM for Quantization Noise Cancellation. ISSCC Haoming Zhang, Yuyang Zhu, Masaru Osada, Tetsuya Iizuka
2025	J	`jnl`	A Fractional-N Cascaded PLL With MMD-Based Quantization-Error Cancellation. IEEE J. Solid State Circuits Haoming Zhang, Yuyang Zhu, Masaru Osada, Tetsuya Iizuka
2025	J	`jnl`	A Harmonic-Mixer-Based Fractional-N PLL Employing Voltage-Domain Feed-Forward Noise Cancellation. IEEE J. Solid State Circuits Haoming Zhang, Masaru Osada, Yuyang Zhu, Tetsuya Iizuka
2025	J	`jnl`	An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC. Circuits Syst. Signal Process. Shuowei Li, Zunsong Yang, Tetsuya Iizuka
2025	J	`jnl`	Analysis of Intrinsic Quantizer Non-Linearity in ΔΣ ADCs. IEICE Trans. Electron. Yo Kumano, Tetsuya Iizuka
2025	J	`jnl`	CMOS Implementation of Field Programmable Spiking Neural Network for Hardware Reservoir Computing. CoRR Ckristian Duran, Nanako Kimura, Zolboo Byambadorj, Tetsuya Iizuka
2025	J	`jnl`	Comparative Analysis of Interleaving Schemes in High-Speed Digital-to-Analog Converters. IEICE Trans. Electron. Yunjie Chen, Koji Asami, Zolboo Byambadorj, Akio Higo, Tetsuya Iizuka
2025	—	`conf`	Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave Detection. ASP-DAC Yuyang Zhu, Zunsong Yang, Zhenyu Cheng, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka
2025	—	`conf`	Design of a 7.2-GHz CMOS Receiver Front-end for One-chip Transponders in Deep Space Probes. ASP-DAC Sota Kano, Naoto Usami, Atsushi Tomiki, Tetsuya Iizuka
2025	J	`jnl`	Experimental Demonstration of Planar Near-Field to Far-Field Transformation With Probe Correction Technique. IEEE Access Zolboo Byambadorj, Koji Asami, Akio Higo, Nguyen Ngoc Mai Khanh, Sheng Guo, Hiroyuki Mineo, Natsuki Shiota, Tetsuya Iizuka
2025	J	`jnl`	Fully-Standard-Cell-Based Synthesizable Charge-Redistribution SAR ADCs and P&R-Based Layout Automation Framework. IEEE Access Shuowei Li, Ckristian Duran, Ritaro Takenaka, Tetsuya Iizuka
2025	J	`jnl`	Hardware-friendly implementation of physical reservoir computing with CMOS-based time-domain analog spiking neurons. Neuromorph. Comput. Eng. Nanako Kimura, Ckristian Duran, Zolboo Byambadorj, Ryosho Nakane, Tetsuya Iizuka
2025	J	`jnl`	Optimization of DTC-Based and Harmonic-Mixer-Based Fractional-N PLLs: Comparative Analysis of Jitter and Power Trade-Offs. IEEE Trans. Circuits Syst. I Regul. Pap. Yuyang Zhu, Masaru Osada, Haoming Zhang, Tetsuya Iizuka
2025	—	`conf`	TDR-Based S-Parameter Estimation of Signal Path to DUT Utilizing Built-In Driver and Comparator of ATE. ATS Kazuki Shirahata, Masahiro Ishida, Koji Asami, Toru Nakura, Akio Higo, Tetsuya Iizuka
2024	J	`jnl`	150GHz Fundamental Oscillator Utilizing Transmission-Line-Based Inter-Stage Matching in 130nm SiGe BiCMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sota Kano, Tetsuya Iizuka
2024	—	`conf`	A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur. VLSI Technology and Circuits Tianle Chen, Hongyu Ren, Zunsong Yang, Yunbo Huang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li
2024	J	`jnl`	A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering. IEEE J. Solid State Circuits Masaru Osada, Zule Xu, Zunsong Yang, Tetsuya Iizuka
2024	J	`jnl`	A Single Ring-Oscillator-Based Test Structure for Timing Characterization of Dynamic Circuit. IEEE Trans. Very Large Scale Integr. Syst. Haoming Zhang, Shuowei Li, Tetsuya Iizuka
2024	C	`conf`	A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. ISCAS Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Khai-Duy Nguyen, Tetsuya Iizuka, Trong-Thuc Hoang, Cong-Kha Pham
2024	J	`jnl`	Guest Editorial: Introduction to the Special Section on the 2023 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits Ken Takeuchi, Tetsuya Iizuka, Kazuko Nishimura, Jerald Yoo
2024	J	`jnl`	Hardware-Friendly Implementation of Physical Reservoir Computing with CMOS-based Time-domain Analog Spiking Neurons. CoRR Nanako Kimura, Ckristian Duran, Zolboo Byambadorj, Ryosho Nakane, Tetsuya Iizuka
2024	J	`jnl`	Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuyang Zhu, Zunsong Yang, Masaru Osada, Haoming Zhang, Tetsuya Iizuka
2023	—	`conf`	A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit. ICICDT Yuyang Zhu, Zunsong Yang, Zhenyu Cheng, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka
2023	J	`jnl`	A 79.2-μW 19.5-kHz-BW 94.8-dB-SNDR Fully Dynamic DT ΔΣ ADC Using CLS-Assisted FIA With Sampling Noise Cancellation. IEEE Trans. Circuits Syst. II Express Briefs Akira Matsuoka, Yo Kumano, Tomohiro Nezuka, Yoshikazu Furuta, Tetsuya Iizuka
2023	—	`conf`	A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load. VLSI Technology and Circuits Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka
2023	J	`jnl`	Analysis of SAR ADC Performance Enhancement Utilizing Stochastic Resonance. IEEE Trans. Circuits Syst. II Express Briefs Ryoya Shibata, Yasushi Hotta, Hitoshi Tabata, Tetsuya Iizuka
2023	—	`conf`	Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit. ICICDT Zhenyu Cheng, Zunsong Yang, Yuyang Zhu, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka
2023	—	`conf`	Dynamic Circuit Characterization and a Single Ring-Oscillator-Based Test Structure for Its Timing Parameter Extraction. ICICDT Haoming Zhang, Shuowei Li, Tetsuya Iizuka
2023	—	`conf`	INVITED PAPER: A 4.5-5.4GHz Digital Bang-Bang PLL for Cryogenic Applications. ICTA Haoyuan Gao, Hao Xu, Xinyi Lin, Yan Liu, Zhidong Tang, Xufeng Kou, Xingyu Zhang, Tetsuya Iizuka, Na Yan
2023	—	`conf`	Long-time-constant leaky-integrating oxygen-vacancy drift-diffusion FET for human-interactive spiking reservoir computing. VLSI Technology and Circuits Hisashi Inoue, Hiroto Tamura, Ai Kitoh, Xiangyu Chen, Zolboo Byambadorj, Takeaki Yajima, Yasushi Hotta, Tetsuya Iizuka, Gouhei Tanaka, Isao H. Inoue
2022	—	`conf`	140 GHz Energy-Efficient OOK Receiver using Self-Mixer-Based Power Detector in 65nm CMOS. ICICDT Nguyen Ngoc Mai Khanh, Daisuke Yamazaki, Tetsuya Iizuka
2022	J	`jnl`	4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. IEICE Trans. Electron. Tetsuya Iizuka, Meikan Chin, Toru Nakura, Kunihiro Asada
2022	—	`conf`	A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. VLSI Technology and Circuits Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka
2022	C	`conf`	A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal. ISCAS Ryoya Shibata, Zule Xu, Yasushi Hotta, Hitoshi Tabata, Tetsuya Iizuka
2022	—	`conf`	An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering. ESSCIRC Masaru Osada, Zule Xu, Tetsuya Iizuka
2022	J	`jnl`	Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation. IEEE Trans. Circuits Syst. I Regul. Pap. Masaru Osada, Zule Xu, Ryoya Shibata, Tetsuya Iizuka
2022	J	`jnl`	CMOS-based area-and-power-efficient neuron and synapse circuits for time-domain analog spiking neural networks. CoRR Xiangyu Chen, Takeaki Yajima, Hisashi Inoue, Isao H. Inoue, Zolboo Byambadorj, Tetsuya Iizuka
2022	J	`jnl`	Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs Akira Matsuoka, Tomohiro Nezuka, Tetsuya Iizuka
2022	J	`jnl`	High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing. IEEE Trans. Circuits Syst. I Regul. Pap. Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
2021	—	`conf`	A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. VLSI Circuits Zule Xu, Masaru Osada, Tetsuya Iizuka
2021	—	`conf`	A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW. ESSCIRC Tetsuya Iizuka, Hao Xu, Asad A. Abidi
2021	J	`jnl`	An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC. IEEE Trans. Very Large Scale Integr. Syst. Zule Xu, Naoki Ojima, Shuowei Li, Tetsuya Iizuka
2021	—	`conf`	Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper. ICICDT Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Kunihiro Asada
2020	J	`jnl`	11 Gb/s 140 GHz OOK modulator with 24.6 dB isolation utilising cascaded switch and amplifier-based stages in 65 nm bulk CMOS. IET Circuits Devices Syst. Daisuke Yamazaki, Yoshitaka Otsuki, Takafumi Hara, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka
2020	—	`conf`	A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. VLSI Circuits Masaru Osada, Zule Xu, Tetsuya Iizuka
2020	J	`jnl`	A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters. IEEE Trans. Circuits Syst. Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
2020	J	`jnl`	Theoretical Analysis of Noise Figure for Modulated Wideband Converter. IEEE Trans. Circuits Syst. I Regul. Pap. Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
2020	—	`conf`	Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing. ATS Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka
2019	—	`conf`	A 0.0053-mm NEWCAS Naoki Ojima, Zule Xu, Tetsuya Iizuka
2019	J	`jnl`	A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS. IEICE Electron. Express Yoshitaka Otsuki, Daisuke Yamazaki, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka
2019	J	`jnl`	A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. IEEE Trans. Very Large Scale Integr. Syst. Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada
2019	J	`jnl`	A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. IEICE Electron. Express Wang Jing, Tetsuya Iizuka, Zule Xu, Toru Nakura
2019	J	`jnl`	Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. IEEE Trans. Instrum. Meas. Daigo Takahashi, Tetsuya Iizuka, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada
2019	J	`jnl`	Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. IEICE Electron. Express Tetsuya Iizuka, Kai Xu, Xiao Yang, Toru Nakura, Kunihiro Asada
2018	—	`conf`	A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. VLSI-SoC (Selected Papers) Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2018	—	`conf`	A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. MWSCAS Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada
2018	C	`conf`	A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. VLSI-SoC Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2018	J	`jnl`	A Unified Analysis of the Signal Transfer Characteristics of a Single-Path FET-R-C Circuit. IEICE Trans. Electron. Tetsuya Iizuka, Asad A. Abidi
2018	J	`jnl`	Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. Tetsuya Iizuka, Takaaki Ito, Asad A. Abidi
2018	J	`jnl`	Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. J. Electron. Test. Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
2018	J	`jnl`	Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation. IEEE Trans. Instrum. Meas. Nguyen Ngoc Mai Khanh, Shigeru Nakajima, Tetsuya Iizuka, Yoshio Mita, Kunihiro Asada
2018	J	`jnl`	Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2018	J	`jnl`	Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. IEICE Trans. Electron. Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada
2018	J	`jnl`	Time-domain approach for analog circuits in deep sub-micron LSI. IEICE Electron. Express Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda
2018	J	`jnl`	Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. IEICE Trans. Electron. Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. ASP-DAC Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. ICECS Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	J	`jnl`	A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. IEICE Trans. Electron. Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	J	`jnl`	A PLL Compiler from Specification to GDSII. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. IEEE SENSORS Xiao Yang, Kai Xu, Tetsuya Iizuka, Toru Nakura, Hongbo Zhu, Kunihiro Asada
2017	—	`conf`	A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. ICECS Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. ICECS Ryuichi Enomoto, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	—	`conf`	CMOS-on-quartz pulse generator for low power applications. ASP-DAC Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	J	`jnl`	Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	B	`conf`	Extension of power supply impedance emulation method on ATE for multiple power domain. ETS Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	High Spatial Resolution Detection Method for Point Light Source in Scintillator. Computational Imaging Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	—	`conf`	Impulse signal generator based on current-mode excitation and transmission line resonator. NEWCAS Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	—	`conf`	Session 4 - Modeling and measurement of mixed-signal circuits. CICC Colin McAndrew, Tetsuya Iizuka
2016	—	`conf`	A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. ESSCIRC Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada
2016	—	`conf`	A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. A-SSCC Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada
2016	J	`jnl`	An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. J. Circuits Syst. Comput. Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2016	A	`conf`	Analytical design optimization of sub-ranging ADC based on stochastic comparator. DATE Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2016	—	`conf`	Experimental demonstration of stochastic comparators for fine resolution ADC without calibration. ICECS Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada
2016	J	`jnl`	FET-R-C Circuits: A Unified Treatment - Part I: Signal Transfer Characteristics of a Single-Path. IEEE Trans. Circuits Syst. I Regul. Pap. Tetsuya Iizuka, Asad A. Abidi
2016	J	`jnl`	FET-R-C Circuits: A Unified Treatment - Part II: Extension to Multi-Paths, Noise Figure, and Driving-Point Impedance. IEEE Trans. Circuits Syst. I Regul. Pap. Tetsuya Iizuka, Asad A. Abidi
2016	A	`conf`	Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. ITC Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
2016	—	`conf`	Resonant power supply noise reduction using a triangular active charge injection. ICECS Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2015	J	`jnl`	A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs. IEEE Trans. Instrum. Meas. Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada
2015	—	`conf`	A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. A-SSCC Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2015	C	`conf`	An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. DDECS Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2015	—	`conf`	F1: High-speed interleaved ADCs. ISSCC Stephane Le Tuai, Borivoje Nikolic, Tetsuya Iizuka, Ichiro Fujimori
2015	—	`conf`	Session 12 - Tutorial - beyond CMOS: Large area electronics-concepts and prospects. CICC Robert C. Aitken, Tetsuya Iizuka
2015	—	`conf`	Session 3 - Optical interconnect and reliability enhancement techniques. CICC Tetsuya Iizuka, Takahiro J. Yamaguchi
2015	—	`conf`	Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. NORCAS Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2014	J	`jnl`	A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2014	—	`conf`	Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration. CICC Manoj Sachdev, Tetsuya Iizuka
2014	B	`conf`	High-resolution measurement of magnetic field generated from cryptographic LSIs. SAS Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada
2013	—	`conf`	A Pulse Width controlled PLL and its automated design flow. ICECS Norihito Tohge, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2013	—	`conf`	A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. ISPD Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2013	—	`conf`	A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC. CICC Tetsuya Iizuka, Satoshi Miura, Yohei Ishizone, Yoshimichi Murakami, Kunihiro Asada
2013	—	`conf`	An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. CICC Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada
2013	J	`jnl`	High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2013	—	`conf`	High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. ASP-DAC Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada
2013	—	`conf`	Session 26 overview: High-speed data converters. ISSCC Boris Murmann, Tetsuya Iizuka
2012	—	`conf`	7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. CICC Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada
2012	J	`jnl`	A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology. IEICE Trans. Electron. Tetsuya Iizuka, Satoshi Miura, Ryota Yamamoto, Yutaka Chiba, Shunichi Kubo, Kunihiro Asada
2012	J	`jnl`	All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator. IEICE Trans. Electron. Tetsuya Iizuka, Kunihiro Asada
2012	J	`jnl`	Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. IEICE Trans. Electron. Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2012	—	`conf`	Impact of All-Digital PLL on SoC Testing. Asian Test Symposium Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2011	J	`jnl`	1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Trans. Electron. Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. ESSCIRC Kazutoshi Kodama, Tetsuya Iizuka, Kunihiro Asada
2011	J	`jnl`	All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Trans. Electron. Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2011	J	`jnl`	All-digital ramp waveform generator for two-step single-slope ADC. IEICE Electron. Express Tetsuya Iizuka, Kunihiro Asada
2011	C	`conf`	An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. DDECS Tetsuya Iizuka, Kunihiro Asada
2011	J	`jnl`	Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Trans. Electron. Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2011	J	`jnl`	Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation. J. Next Gener. Inf. Technol. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2010	—	`conf`	All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. ESSCIRC Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2010	C	`conf`	Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. DDECS Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2010	—	`conf`	Time-to-digital converter based on time difference amplifier with non-linearity calibration. ESSCIRC Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2007	—	`conf`	OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. ISQED Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2007	—	`conf`	Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-meter CMOS. ICECS Kenichiro Kurihara, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2007	J	`jnl`	Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. IEEE Trans. Very Large Scale Integr. Syst. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2006	C	`conf`	Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. ISCAS Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2006	—	`conf`	Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement. ICECS Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2006	A	`conf`	Timing-driven cell layout de-compaction for yield optimization by critical area minimization. DATE Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2005	J	`jnl`	Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2005	—	`conf`	Exact minimum-width transistor placement without dual constraint for CMOS cells. ACM Great Lakes Symposium on VLSI Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2005	J	`jnl`	Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2004	—	`conf`	Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. ISQED Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2004	—	`conf`	High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. ASP-DAC Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2000	—	`conf`	Mining sequential patterns including time intervals. Data Mining and Knowledge Discovery: Theory, Tools, and Technology Mariko Yoshida, Tetsuya Iizuka, Hisako Shiohara, Masanori Ishiguro
1998	B	`conf`	Automatic Visualization Method for Visual Data Mining. PAKDD Yuichi Iizuka, Hisako Shiohara, Tetsuya Iizuka, Seiji Isobe
1990	J	`jnl`	A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC. IEEE J. Solid State Circuits Kazutaka Nogami, Takayasu Sakurai, Kazuhiro Sawada, Kenji Sakaue, Yuichi Miyazawa, Shinichi Tanaka, Ypocjo Hiruta, Katsuto Katoh, Toshinari Takayanagi, Tsukasa Shirotori, Yasuo Itoh, Masanori Uchida, Tetsuya Iizuka
1989	J	`jnl`	A 32 kbyte integrated cache memory. IEEE J. Solid State Circuits Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Tsukasa Shirotori, Toshinari Takayanagi, Tetsuya Iizuka, Takeo Maeda, Jinichi Matsunaga, Hiromichi Fuji, Kenji Maeguchi, Kiyoshi Kobayashi, Tomoyuki Ando, Yoshiki Hayakashi, Akio Miyoshi, Kazuyuki Sato
1988	J	`jnl`	A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode. IEEE J. Solid State Circuits Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Katsuhiko Sato, Tsukasa Shirotori, Masakazu Kakuma, Shigeru Morita, Masaaki Kinugawa, Tetsuya Asami, Kazuhito Narita, Jun-Ichi Matsunaga, Akira Higuchi, Mitsuo Isobe, Tetsuya Iizuka
1988	C	`conf`	Large memory embedded ASICs. ICCD Tetsuya Iizuka, Takayasu Sakurai, J. Matsunaga, K. Maeguchi, K. Kawagai, T. Kobayashi, Y. Shiotari, K. Kobayashi, T. Miyoshi