Tetsuya Iida

12 papers C 2Journal 6Unranked 4
YearRankTypeTitle / Venue / Authors
2012 — conf
A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADCs.
ISSCC
Toshihisa Watabe, Kazuya Kitamura, Takehide Sawamoto, Tomohiko Kosugi, Tomoyuki Akahori, Tetsuya Iida, Keigo Isobe, Takashi Watanabe, Hiroshi Shimamoto, Hiroshi Ohtake, Satoshi Aoyama, Shoji Kawahito, Norifumi Egami
2012 J jnl
A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC.
IEEE J. Solid State Circuits
Min-Woong Seo, Sungho Suh, Tetsuya Iida, Taishi Takasawa, Keigo Isobe, Takashi Watanabe, Shinya Itoh, Keita Yasutomi, Shoji Kawahito
2011 — conf
An 80μVrms-temporal-noise 82dB-dynamic-range CMOS Image Sensor with a 13-to-19b variable-resolution column-parallel folding-integration/cyclic ADC.
ISSCC
Min-Woong Seo, Sungho Suh, Tetsuya Iida, Hiroshi Watanabe, Taishi Takasawa, Tomoyuki Akahori, Keigo Isobe, Takashi Watanabe, Shinya Itoh, Shoji Kawahito
2011 J jnl
Strategic multi-store opening under financial constraint.
Eur. J. Oper. Res.
Tetsuya Iida, Nobuo Matsubayashi
2007 J jnl
Special Section on Analog Circuits and Related SoC Integration Technologies.
IEICE Trans. Electron.
Tetsuya Iida
2005 — conf
A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS.
CICC
Hirotomo Ishii, Ken Tanabe, Tetsuya Iida
2000 C conf
A straightforward design of mismatch-shaped multi-bit ΔΣ D/A systems.
ISCAS
Zdzislaw Czarnul, K. Oda, Tetsuya Iida
1998 J jnl
A third-order ΔΣ modulator using second-order noise-shaping dynamic element matching.
IEEE J. Solid State Circuits
Akira Yasuda, Hiroshi Tanimoto, Tetsuya Iida
1997 — conf
A current-mode, 3 V, 20 MHz, 9-bit equivalent CMOS sample-and-hold circuit.
ASP-DAC
Yasuhiro Sugimoto, Tetsuya Iida
1996 J jnl
A feedforward technique with frequency-dependent current mirrors for a low-voltage wideband amplifier.
IEEE J. Solid State Circuits
Tetsuro Itakura, Tetsuya Iida
1994 C conf
Principles of nonlinearity Cancellation in Linear MOS Systems using MRC Circuits.
ISCAS
Zdzislaw Czarnul, Shigetaka Takagi, Nobuo Fujii, Tetsuya Iida, Takeshi Yanagisawa
1992 J jnl
Neuro chips with on-chip back-propagation and/or Hebbian learning.
IEEE J. Solid State Circuits
Takeshi Shima, Tomohisa Kimura, Yukio Kamatani, Tetsuro Itakura, Yasuhiko Fujita, Tetsuya Iida