Tetsuya Hirose

115 papers A* 1B 3C 21Journal 52Unranked 38

Year	Rank	Type	Title / Venue / Authors
2026	C	`conf`	A Battery-Free Wireless EEG Transmission System Using Compressed Sensing and Powered by Body-Ambient Temperature Difference: Outdoor Demonstration at Expo 2025. ICCE Daisuke Kanemoto, Kazane Yoshimoto, Shodai Motomochi, Tetsuya Hirose
2025	—	`conf`	20.1 A 3.5×3.5mm ISSCC Kotaro Naruse, Naru Kato, Takuma Matsumori, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Gaku Imamura, Genki Yoshikawa, Constantine Sideris, Noriyuki Miura
2025	C	`conf`	Design Guidelines for Noise in a Low-Noise Amplifier Using EEG Signals as a Basis Matrix in Compressed Sensing System. ICCE Riku Matsubara, Daisuke Kanemoto, Tetsuya Hirose
2025	C	`conf`	Development of Low-power and High-accuracy Wireless EEG Transmission System Using Compressed Sensing with an EEG Basis. ISCAS Daisuke Kanemoto, Eichi Takimoto, Tetsuya Hirose
2025	—	`conf`	Low quiescent current LDO with FBPEC to improve PSRR specific frequency band for wearable EEG recording devices. ASP-DAC Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose
2025	C	`conf`	Low-power and Low-noise Amplifier with Intermittent Operation for Compressed Sensing in EEG Measurement Systems. ISCAS Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose
2025	C	`conf`	Noise-Masking Cryptosystem Using Watermark and Chain Generation for EEG Measurement with Compressed Sensing. ICCE Tomoya Yamamoto, Daisuke Kanemoto, Tetsuya Hirose
2025	C	`conf`	Sub-50-mV Static Flip-Flop Consisting of Recursive Stacking Body-Bias Logic Gates for Extremely Low-Voltage VLSIs. ISCAS Shintaro Sumi, Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose
2025	—	`conf`	Ultra Low-power Capacitively-coupled Chopper Amplifier Focusing on the Sparsity of Compressed Sensing for EEG Recording. ASP-DAC Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose
2024	C	`conf`	Noise-Masking Cryptosystem Using Watermark and Chain Generation for EEG Measurement with Compressed Sensing. ICCE Ryota Tsunaga, Daisuke Kanemoto, Tetsuya Hirose
2024	J	`jnl`	Programmable Differential Bandgap Reference Circuit for Ultra-Low-Power CMOS LSIs. IEICE Trans. Electron. Yoshinori Itotagawa, Koma Atsumi, Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose
2024	C	`conf`	Reducing Power Consumption in LNA by Utilizing EEG Signals as Basis Matrix in Compressed Sensing. ISCAS Riku Matsubara, Daisuke Kanemoto, Tetsuya Hirose
2024	J	`jnl`	Sub-60-mV Charge Pump and its Driver Circuit for Extremely Low-Voltage Thermoelectric Energy Harvesting. IEICE Trans. Electron. Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose
2024	C	`conf`	Utilizing Previously Acquired BSBL Algorithm Parameters in the Compressed Sensing Framework for EEG Measurements. ICCE Takuya Miyata, Daisuke Kanemoto, Tetsuya Hirose
2023	C	`conf`	A Programmable Differential Bandgap Reference for Ultra-Low-Power IoT Edge Node Devices. ISCAS Yoshinori Itotagawa, Koma Atsumi, Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose
2023	—	`conf`	A Triturated Sensing System. ISSCC Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata
2023	C	`conf`	EEG Measurements with Compressed Sensing Utilizing EEG Signals as the Basis Matrix. ISCAS Daisuke Kanemoto, Tetsuya Hirose
2023	C	`conf`	Random Undersampling Wireless EEG Measurement Device using a Small TEG. ISCAS Takuya Miyata, Daisuke Kanemoto, Tetsuya Hirose
2023	—	`conf`	Sub-30-mV-Supply, Fully Integrated Ring Oscillator Consisting of Recursive Stacking Body-Bias Inverters for Extremely Low-Voltage Energy Harvesting. ESSCIRC Hikaru Sebe, Tomohisa Okumura, Shintaro Sumi, Daisuke Kanemoto, Po-Hung Chen, Tetsuya Hirose
2022	J	`jnl`	Compressed Sensing EEG Measurement Technique with Normally Distributed Sampling Series. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuki Okabe, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose
2022	J	`jnl`	Image Quality Improvement for Capsule Endoscopy Based on Compressed Sensing with K-SVD Dictionary Learning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuuki Harada, Daisuke Kanemoto, Takahiro Inoue, Osamu Maida, Tetsuya Hirose
2022	C	`conf`	Sub-50-mV Charge Pump and its Driver for Extremely Low-Voltage Thermal Energy Harvesting. ISCAS Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose
2021	J	`jnl`	A 35-mV supply ring oscillator consisting of stacked body bias inverters for extremely low-voltage LSIs. IEICE Electron. Express Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose
2021	J	`jnl`	Multi-Category Image Super-Resolution with Convolutional Neural Network and Multi-Task Learning. IEICE Trans. Inf. Syst. Kazuya Urazoe, Nobutaka Kuroki, Yu Kato, Shinya Ohtani, Tetsuya Hirose, Masahiro Numa
2020	J	`jnl`	A 115× Conversion-Ratio Thermoelectric Energy-Harvesting Battery Charger for the Internet of Things. IEEE Trans. Circuits Syst. Ming-Jie Chung, Tetsuya Hirose, Takahito Ono, Po-Hung Chen
2020	—	`conf`	A 34-mV Startup Ring Oscillator Using Stacked Body Bias Inverters for Extremely Low-Voltage Thermoelectric Energy Harvesting. NEWCAS Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose
2020	J	`jnl`	An 11.8 nA ultra-low power active diode using a hysteresis common gate comparator for low-power energy harvesting systems. IEICE Electron. Express Kaori Matsumoto, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose
2020	J	`jnl`	Design of Switched-Capacitor Voltage Boost Converter for Low-Voltage and Low-Power Energy Harvesting Systems. IEICE Trans. Electron. Tetsuya Hirose, Yuichiro Nakazawa
2020	—	`conf`	Detecting tampered regions in JPEG images via CNN. NEWCAS Kunihiko Taya, Nobutaka Kuroki, Naoto Takeda, Tetsuya Hirose, Masahiro Numa
2020	J	`jnl`	Improvement of Luminance Isotropy for Convolutional Neural Networks-Based Image Super-Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kazuya Urazoe, Nobutaka Kuroki, Yu Kato, Shinya Ohtani, Tetsuya Hirose, Masahiro Numa
2019	—	`conf`	An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. A-SSCC Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto
2019	—	`conf`	Sub-0.1V Input, Low-Voltage CMOS Driver Circuit for Multi-Stage Switched Capacitor Voltage Boost Converter. ICECS Masaya Nishi, Yuichiro Nakazawa, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose
2018	—	`conf`	A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes. NEWCAS Ryo Shirai, Tetsuya Hirose, Masanori Hashimoto
2018	J	`jnl`	A Sub-1-µs Start-Up Time, Fully-Integrated 32-MHz Relaxation Oscillator for Low-Power Intermittent Systems. IEICE Trans. Electron. Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa
2018	C	`conf`	An ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems. VLSI-SoC Kaori Matsumoto, Tetsuya Hirose, Hiroki Asano, Yuto Tsuji, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa
2018	C	`conf`	Analytical Study of Multi-stage Switched-Capacitor Voltage Boost Converter for Ultra-low Voltage Energy Harvesting. ISCAS Yuichiro Nakazawa, Tetsuya Hirose, Toshihiro Ozaki, Yuto Tsuji, Shuto Kanzaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa
2018	—	`conf`	Switched-Capacitor Voltage Buck Converter with Step-Down-Ratio and Clock-Frequency Controllers for Ultra-Low-Power IoT Devices. ICECS Shuto Kanzaki, Tetsuya Hirose, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa
2017	—	`conf`	A 0.1-0.6 V input range voltage boost converter with low-leakage driver for low-voltage energy harvesting. ICECS Yuto Tsuji, Tetsuya Hirose, Toshihiro Ozaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa
2017	J	`jnl`	An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs. IEEE Trans. Circuits Syst. I Regul. Pap. Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Kyohei Shinonaga, Nobutaka Kuroki, Masahiro Numa
2017	C	`conf`	An area-efficient, 0.022-mm2, fully integrated resistor-less relaxation oscillator for ultra-low power real-time clock applications. ISCAS Hiroki Asano, Tetsuya Hirose, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa
2017	—	`conf`	An ultra-low-power supercapacitor voltage monitoring system for low-voltage energy harvesting. ICECS Takanori Sato, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa
2017	J	`jnl`	Multi-Channel Convolutional Neural Networks for Image Super-Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinya Ohtani, Yu Kato, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa
2017	C	`conf`	Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node. ISCAS Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto
2017	—	`conf`	Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems. ASP-DAC Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa
2017	—	`conf`	Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes. ASICON Masanori Hashimoto, Ryo Shirai, Yuichi Itoh, Tetsuya Hirose
2016	—	`conf`	A 0.38-μW stand-by power, 50-nA-to-1-mA load current range DC-DC converter with self-biased linear regulator for ultra-low power battery management. A-SSCC Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa
2016	—	`conf`	A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stability. ESSCIRC Hiroki Asano, Tetsuya Hirose, Keishi Tsubaki, Taro Miyoshi, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa
2016	J	`jnl`	A Highly Efficient Switched-Capacitor Voltage Boost Converter with Nano-Watt MPPT Controller for Low-Voltage Energy Harvesting. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa
2016	—	`conf`	A fully integrated, 1-µs start-up time, 32-MHz relaxation oscillator for low-power intermittent systems. NEWCAS Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa
2016	J	`jnl`	Fully-Integrated High-Conversion-Ratio Dual-Output Voltage Boost Converter With MPPT for Low-Voltage Energy Harvesting. IEEE J. Solid State Circuits Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa
2016	—	`conf`	Image super-resolution with multi-channel convolutional neural networks. NEWCAS Yu Kato, Shinya Ohtani, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa
2015	C	`conf`	A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs. ISCAS Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Nobutaka Kuroki, Masahiro Numa
2015	—	`conf`	A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters. ASP-DAC Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa
2015	J	`jnl`	A 32-kHz Real-Time Clock Oscillator with On-Chip PVT Variation Compensation Circuit for Ultra-Low Power MCUs. IEICE Trans. Electron. Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2015	—	`conf`	A fully-integrated, high-conversion-ratio and dual-output voltage boost converter with MPPT for low-voltage energy harvesting. A-SSCC Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa
2015	J	`jnl`	An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
2015	J	`jnl`	Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation. IEICE Electron. Express Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
2014	—	`conf`	A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters. ESSCIRC Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa
2014	—	`conf`	A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis. NEWCAS Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
2014	J	`jnl`	A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit. IEICE Trans. Electron. Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa
2013	J	`jnl`	1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs. IEEE J. Solid State Circuits Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2013	J	`jnl`	A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation. IEICE Electron. Express Igors Homjakovs, Tetsuya Hirose, Yuji Osaki, Masanori Hashimoto, Takao Onoye
2013	—	`conf`	A 32.55-kHz, 472-nW, 120ppm/°C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application. ESSCIRC Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2013	J	`jnl`	Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Igors Homjakovs, Masanori Hashimoto, Tetsuya Hirose, Takao Onoye
2012	—	`conf`	A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator. ICECS Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa
2012	J	`jnl`	A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs. IEEE J. Solid State Circuits Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2012	—	`conf`	A low-power single-slope analog-to-digital converter with digital PVT calibration. ICECS Yuji Osaki, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa
2012	—	`conf`	A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs. ESSCIRC Yumiko Tsuruya, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa, Osamu Kobayashi
2012	—	`conf`	Signal-dependent analog-to-digital converter based on MINIMAX sampling. ISOCC Igors Homjakovs, Masanori Hashimoto, Takao Onoye, Tetsuya Hirose
2011	—	`conf`	A 18.9-nA standby current comparator with adaptive bias current generator. A-SSCC Kosuke Isono, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa
2011	—	`conf`	A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder. ASP-DAC Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2011	—	`conf`	A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs. ESSCIRC Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2011	J	`jnl`	A wide input voltage range level shifter circuit for extremely low-voltage digital LSIs. IEICE Electron. Express Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2011	J	`jnl`	Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique. IEICE Trans. Electron. Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa
2011	J	`jnl`	Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit. IEICE Trans. Electron. Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa
2011	—	`conf`	Ultra-low power and low voltage circuit design for next-generation power-aware LSI applications. ISOCC Tetsuya Hirose
2010	J	`jnl`	A 1-muhboxW 600- hboxppm/ IEEE Trans. Circuits Syst. II Express Briefs Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2010	—	`conf`	A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities. ESSCIRC Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa
2010	J	`jnl`	An Error Diagnosis Technique Based on Clustering of Elements. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kosuke Shioki, Narumi Okada, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2010	J	`jnl`	An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs. IEICE Trans. Electron. Yusuke Tsugita, Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2010	C	`conf`	Super-resolution technique for thermography with dual-camera system. ISCAS Shingo Chikamatsu, Tomohiro Nakaya, Masakazu Kouda, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa
2009	J	`jnl`	A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs. IEEE J. Solid State Circuits Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2009	—	`conf`	A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. ASP-DAC Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2009	J	`jnl`	A Look-ahead Active Body-biasing scheme for SOI-SRAM with dynamic IEICE Electron. Express Kayoko Seto, Masaaki Iijima, Tetsuya Hirose, Masahiro Numa, Akira Tada, Takashi Ipposhi
2009	J	`jnl`	An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
2009	J	`jnl`	Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2009	C	`conf`	On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. ISCAS Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose
2009	J	`jnl`	Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2008	—	`conf`	A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits. ESSCIRC Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2008	J	`jnl`	Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2008	J	`jnl`	On Digital LSI Circuits Exploiting Collision-Based Fusion Gates. Int. J. Unconv. Comput. Kazuhito Yamada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2008	J	`jnl`	Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs. IEICE Electron. Express Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2007	J	`jnl`	A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. Int. J. Bifurc. Chaos Motoyoshi Takahashi, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2007	J	`jnl`	A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. Neurocomputing Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya
2007	J	`jnl`	An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2007	—	`conf`	Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. ICONIP (2) Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2007	J	`jnl`	CMOS Smart Sensor for Monitoring the Quality of Perishables. IEEE J. Solid State Circuits Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2007	C	`conf`	Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. ISCAS Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2007	B	`conf`	Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. IJCNN Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2006	J	`jnl`	A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2006	J	`jnl`	A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. Int. J. Bifurc. Chaos Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya
2006	J	`jnl`	Power-supply circuits for ultralow-power subthreshold MOS-LSIs. IEICE Electron. Express Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2005	J	`jnl`	A CMOS IF Variable Gain Amplifier with Exponential Gain Control. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sungwoo Cha, Tetsuya Hirose, Masaki Haruoka, Toshimasa Matsuoka, Kenji Taniguchi
2005	J	`jnl`	A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. Parallel Algorithms Appl. Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya
2005	J	`jnl`	Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model. Int. J. Unconv. Comput. Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya
2005	B	`conf`	Analog current-mode CMOS implementation of central pattern generator for robot locomotion. IJCNN Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2005	J	`jnl`	Ultralow-Power Current Reference Circuit with Low Temperature Dependence. IEICE Trans. Electron. Tetsuya Hirose, Toshimasa Matsuoka, Kenji Taniguchi, Tetsuya Asai, Yoshihito Amemiya
2004	J	`jnl`	A MOS circuit for bursting neural oscillators with excitable oregonators. IEICE Electron. Express Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2004	B	`conf`	A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection. IJCNN Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya
2004	J	`jnl`	Atomic configuration of boron pile-up at the Si/SiO2 interface. IEICE Electron. Express Masayuki Furuhashi, Tetsuya Hirose, Hiroshi Tsuji, Masayuki Tachi, Kenji Taniguchi
2004	J	`jnl`	Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. IEICE Electron. Express Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2000	A*	`conf`	A DSM Architecture for a Parallel Computer Cenju-4. HPCA Takeo Hosomi, Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose
1999	—	`conf`	Message Passing Communication in a Parallel Computer Cenju-4. ISHPC Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose, Takeo Hosomi, Hirokazu Takayama, Toshiyuki Nakata
1995	J	`jnl`	Architecture of a parallel machine: Cenju-3. Syst. Comput. Jpn. Tsutomu Maruyama, Yasushi Kanoh, Tetsuya Hirose, Kazuhiro Muramatsu, Toshiyuki Nakata, Yoshihiro Asano, Yu Inamura
1993	—	`conf`	A Fine-Grained Parallel Genetic Algorithm for Distributed Parallel Systems. ICGA Tsutomu Maruyama, Tetsuya Hirose, Akihiko Konagaya