Tetsuya Asai - RankMe

142 papers B 12C 7Misc 2Journal 71Unranked 46

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Co-Optimization of Models and Hardware for Neural Network Inference in Variable-Parallelism Processor. CANDARW Yu Inoue, Atsushi Hori, Takao Marukame, Tetsuya Asai, Alexandre Schmid, Kota Ando
2025	J	`jnl`	Expanding detection bandwidth via a photonic reservoir for ultrafast optical sensing. CoRR Yuito Ito, Tomoaki Niiyama, Tetsuya Asai, Gouhei Tanaka, Atsushi Uchida, Satoshi Sunada
2024	B	`conf`	Edge AI Online Training Architecture Using Multi-Phase-Quantization Optimizer. IJCNN Itsuki Akeno, Hiiro Yamazaki, Tetsuya Asai, Kota Ando
2024	J	`jnl`	Extending Binary Neural Networks to Bayesian Neural Networks with Probabilistic Interpretation of Binary Weights. IEICE Trans. Inf. Syst. Taisei Saito, Kota Ando, Tetsuya Asai
2024	B	`conf`	Out-of-distribution Data Detection using Bayesian Convolutional Neural Network with Variational Inference. IJCNN Koki Minagawa, Taisei Saito, Sena Kojima, Kota Ando, Tetsuya Asai
2024	J	`jnl`	SPCTRE: sparsity-constrained fully-digital reservoir computing architecture on FPGA. Int. J. Parallel Emergent Distributed Syst. Yuki Abe, Kohei Nishida, Kota Ando, Tetsuya Asai
2022	J	`jnl`	Holmes: A Hardware-Oriented Optimizer Using Logarithms. IEICE Trans. Inf. Syst. Yoshiharu Yamagishi, Tatsuya Kaneko, Megumi Akai-Kasaya, Tetsuya Asai
2022	J	`jnl`	Performance of reservoir computing in a random network of single-walled carbon nanotubes complexed with polyoxometalate. Neuromorph. Comput. Eng. Megumi Akai-Kasaya, Yuki Takeshima, Shaohua Kan, Kohei Nakajima, Takahide Oya, Tetsuya Asai
2022	J	`jnl`	Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark. IEEE Trans. Circuits Syst. Video Technol. Yafei Ou, Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
2020	J	`jnl`	A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks. Int. J. Netw. Comput. Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda
2020	J	`jnl`	An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA. IEEE Trans. Circuits Syst. Video Technol. Prasoon Ambalathankandy, Masayuki Ikebe, Takayuki Yoshida, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai
2019	—	`conf`	A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators. CANDAR Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2019	—	`conf`	An FPGA Accelerator for Embedded Microcontrollers Implementing a Ternarized Backpropagation Algorithm. ReConFig Tatsuya Kaneko, Hiroshi Momose, Tetsuya Asai
2019	—	`conf`	DeltaNet: Differential Binary Neural Network. ASAP Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2019	J	`jnl`	Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. IEICE Trans. Inf. Syst. Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
2019	J	`jnl`	FPGA-Based Annealing Processor with Time-Division Multiplexing. IEICE Trans. Inf. Syst. Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2019	Misc	`conf`	Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band. DICTA Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
2019	—	`ch.`	Reaction-Diffusion Media with Excitable Oregonators Coupled by Memristors. Handbook of Memristor Networks Tetsuya Asai
2018	C	`conf`	Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions. VCIP Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
2018	—	`conf`	Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. MCSoC Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2018	J	`jnl`	BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
2018	—	`conf`	Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. FPT Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
2018	J	`jnl`	Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. Complex. Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
2018	J	`jnl`	Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. Microprocess. Microsystems Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano
2018	Misc	`conf`	Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. ICASSP Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai
2017	—	`conf`	A Time-Division Multiplexing Ising Machine on FPGAs. HEART Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017	—	`conf`	Accelerating deep learning by binarized hardware. APSIPA Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017	—	`conf`	An image sensor/processor 3D stacked module featuring ThruChip interfaces. ASP-DAC Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura
2017	J	`jnl`	Design and evaluation of single-electron associative memory circuit. Int. J. Parallel Emergent Distributed Syst. Makoto Takano, Tetsuya Asai, Takahide Oya
2017	J	`jnl`	Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation. IEEE Trans. Circuits Syst. II Express Briefs Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani
2017	B	`conf`	Exploring optimized accelerator design for binarized convolutional neural networks. IJCNN Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017	B	`conf`	FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. FPL Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
2017	—	`conf`	In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017	C	`conf`	Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. ISCAS Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid
2017	—	`conf`	Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. CANDAR Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
2017	—	`conf`	Low latency divider using ensemble of moving average curves. ISQED Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura
2017	J	`jnl`	Noise-assisted transmission of spikes in Maeda-Makino artificial neuron arrays. Int. J. Parallel Emergent Distributed Syst. Enrico Prati, Ernesto Giussani, Giorgio Ferrari, Tetsuya Asai
2017	—	`conf`	Quantization Error-Based Regularization in Neural Networks. SGAI Conf. Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2017	J	`jnl`	Special issue of emerging stochastic computing and hardware. Int. J. Parallel Emergent Distributed Syst. Takahide Oya, Tetsuya Asai
2016	—	`conf`	A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors. APCCAS Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2016	—	`conf`	An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions. ReConFig Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2016	—	`conf`	FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting. ReConFig Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2016	C	`conf`	Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. ISCAS Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid
2016	J	`jnl`	Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata. Int. J. Unconv. Comput. Miho Ushida, Alexandre Schmid, Tetsuya Asai, Kazuyoshi Ishimura, Masato Motomura
2016	—	`conf`	Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. ESSCIRC Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura
2015	J	`jnl`	Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation. IEEE Trans. Circuits Syst. II Express Briefs Kamal El-Sankary, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda
2015	J	`jnl`	Enhancing Memcached by Caching Its Data and Functionalities at Network Interface. J. Inf. Process. Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
2015	—	`conf`	Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer. VLSIC Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
2014	—	`conf`	A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator. A-SSCC Itaru Hida, Dahoo Kim, Tetsuya Asai, Masato Motomura
2014	—	`conf`	Achieving higher performance of memcached by caching at network interface. FPT Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
2014	B	`conf`	Caching memcached at reconfigurable network interface. FPL Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
2014	J	`jnl`	Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates. IEICE Electron. Express Lizeth Gonzalez-Carabarin, Tetsuya Asai, Masato Motomura
2014	—	`conf`	Signal Amplification by Circular Single-Electron Oscillator Network with Stochastic Resonance. BICT Hiroyuki Otake, Kazuyoshi Ishimura, Tetsuya Asai, Takahide Oya
2013	—	`conf`	A restricted dynamically reconfigurable architecture for low power processors. ReConFig Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura
2013	—	`conf`	C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join. ARC Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura
2013	—	`conf`	Dynamical system design for silicon neurons using phase reduction approach. EMBC Kazuki Nakada, Keiji Miura, Tetsuya Asai
2013	—	`conf`	Exploiting hardware reconfigurability on window join. HPCS Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Tetsuya Asai, Masato Motomura
2013	—	`conf`	Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. ICECS Katsuki Ohata, Yukitoshi Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda
2012	—	`conf`	Dynamical systems design of nonlinear oscillators using phase reduction approach. APCCAS Kazuki Nakada, Keiji Miura, Tetsuya Asai, Hisa-Aki Tanaka
2012	—	`conf`	Silicon neuron design based on phase reduction analysis. SCIS&ISIS Kazuki Nakada, Keiji Miura, Tetsuya Asai
2011	J	`jnl`	Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator. Int. J. Unconv. Comput. Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya
2010	J	`jnl`	A 1-muhboxW 600- hboxppm/ IEEE Trans. Circuits Syst. II Express Briefs Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2010	J	`jnl`	A CMOS Phase-Shift oscillator Based on the conduction of Heat. J. Circuits Syst. Comput. Takaaki Hirai, Tetsuya Asai, Yoshihito Amemiya
2010	J	`jnl`	A behavioral model of unipolar resistive RAMs and its application to HSPICE integration. IEICE Electron. Express Nobuo Akou, Tetsuya Asai, Takeshi Yanagida, Tomoji Kawai, Yoshihito Amemiya
2010	J	`jnl`	An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs. IEICE Trans. Electron. Yusuke Tsugita, Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2010	—	`conf`	Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits. ICONIP (1) Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya
2010	—	`conf`	High performance sensor-less injection force control considering friction phenomenon. AMC Tetsuya Asai, Yuzuru Ohba, Kiyoshi Ohishi, Katsuyuki Majima, Shiro Urushihara, Koichi Kageyama
2010	J	`jnl`	High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair. IEICE Trans. Electron. Shin'ichi Asai, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya
2009	—	`conf`	A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop. ESSCIRC Ken Ueno, Tetsuya Asai, Yoshihito Amemiya
2009	J	`jnl`	A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs. IEEE J. Solid State Circuits Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2009	—	`conf`	A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. ASP-DAC Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2009	J	`jnl`	A Neuromorphic Single-Electron Circuit for Noise-Shaping Pulse-Density Modulation. Int. J. Nanotechnol. Mol. Comput. Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici
2009	B	`conf`	A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. IJCNN Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici, Yoshihito Amemiya
2009	—	`conf`	Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits. ICONIP (2) Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya
2009	J	`jnl`	Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2009	C	`conf`	Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs. ISCAS Ken Ueno, Tetsuya Asai, Yoshihito Amemiya
2009	—	`ch.`	Nature-inspired Single-electron Computers. Artificial Life Models in Hardware Tetsuya Asai, Takahide Oya
2009	—	`conf`	Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers. ICECS Tomoki Iida, Tetsuya Asai, Eiichi Sano, Yoshihito Amemiya
2009	C	`conf`	On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. ISCAS Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose
2009	—	`conf`	Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution. NanoNet Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya
2009	J	`jnl`	Sensorless Force Control for Injection Molding Machine Using Reaction Torque Observer Considering Torsion Phenomenon. IEEE Trans. Ind. Electron. Yuzuru Ohba, Masaki Sazawa, Kiyoshi Ohishi, Tetsuya Asai, Katsuyuki Majima, Yukio Yoshizawa, Koichi Kageyama
2009	J	`jnl`	Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Utagawa, Tohru Sahashi, Tetsuya Asai, Yoshihito Amemiya
2009	J	`jnl`	Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2009	—	`ch.`	Unconventional Computing, Novel Hardware for. Encyclopedia of Complexity and Systems Science Tetsuya Asai
2008	—	`conf`	A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits. ESSCIRC Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2008	J	`jnl`	Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2008	—	`conf`	Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning. ICONIP (2) Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya
2008	J	`jnl`	On Digital LSI Circuits Exploiting Collision-Based Fusion Gates. Int. J. Unconv. Comput. Kazuhito Yamada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2008	—	`conf`	Stochastic Synchronization and Array-Enhanced Coherence Resonance in a Bio-inspired Chemical Sensor Array. CSE Kazuki Nakada, Jun Igarashi, Tetsuya Asai, Katsumi Tateno, Hatsuo Hayashi, Yoshitaka Ohtubo, Tsutomu Miki, Kiyonori Yoshii
2008	J	`jnl`	Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs. IEICE Electron. Express Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2007	J	`jnl`	A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. Int. J. Bifurc. Chaos Motoyoshi Takahashi, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2007	J	`jnl`	A Single-Electron Reaction-Diffusion Device for Computation of a Voronoi Diagram. Int. J. Unconv. Comput. Takahide Oya, Tetsuya Asai, Yoshihito Amemiya
2007	J	`jnl`	A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. Neurocomputing Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya
2007	J	`jnl`	An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2007	—	`conf`	Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. ICONIP (2) Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2007	J	`jnl`	CMOS Smart Sensor for Monitoring the Quality of Perishables. IEEE J. Solid State Circuits Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2007	J	`jnl`	Discrete Dynamical Systems Consisting of Single-electron Circuits. Int. J. Bifurc. Chaos Andrew Kilinga Kikombo, Takahide Oya, Tetsuya Asai, Yoshihito Amemiya
2007	J	`jnl`	Editorial. Int. J. Parallel Emergent Distributed Syst. Andrew Adamatzky, Christof Teuscher, Tetsuya Asai
2007	C	`conf`	Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. ISCAS Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2007	B	`conf`	Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. IJCNN Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2007	J	`jnl`	Single-electron Circuits Performing Dendritic Pattern Formation with Nature-Inspired Cellular Automata. Int. J. Bifurc. Chaos Takahide Oya, Ikuko N. Motoike, Tetsuya Asai
2007	J	`jnl`	Striped and Spotted Pattern Generation on Reaction-diffusion Cellular Automata - Theory and LSI Implementation. Int. J. Unconv. Comput. Youhei Suzuki, Takahiro Takayama, Ikuko N. Motoike, Tetsuya Asai
2006	J	`jnl`	A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2006	J	`jnl`	A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. Int. J. Bifurc. Chaos Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya
2006	J	`jnl`	Analog Vlsi Implementation of Resonate-and-fire Neuron. Int. J. Neural Syst. Kazuki Nakada, Tetsuya Asai, Hatsuo Hayashi
2006	—	`conf`	Burst Synchronization in Two Pulse-Coupled Resonate-and-Fire Neuron Circuits. IFIP PPAI Kazuki Nakada, Tetsuya Asai, Hatsuo Hayashi
2006	J	`jnl`	Design methodologies for compact logic circuits based on collision-based computing. IEICE Electron. Express Kazuhito Yamada, Ikuko N. Motoike, Tetsuya Asai, Yoshihito Amemiya
2006	C	`conf`	Noise Effects on Performance of Signal Detection in an Analog VLSI Resonate-And Fire Neuron. ISCAS Kazuki Nakada, Jun Igarashi, Tetsuya Asai, Hatsuo Hayashi
2006	J	`jnl`	Power-supply circuits for ultralow-power subthreshold MOS-LSIs. IEICE Electron. Express Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2005	J	`jnl`	A Digital Vision Chip for Early Feature Extraction with Rotated Template-Matching CA. J. Robotics Mechatronics Masayuki Ikebe, Tetsuya Asai
2005	J	`jnl`	A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. Parallel Algorithms Appl. Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya
2005	J	`jnl`	Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices. IEEE Trans. Circuits Syst. I Regul. Pap. Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2005	—	`conf`	Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. ISCAS (3) Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2005	J	`jnl`	Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model. Int. J. Unconv. Comput. Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya
2005	B	`conf`	Analog current-mode CMOS implementation of central pattern generator for robot locomotion. IJCNN Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2005	B	`conf`	Noise performance of single-electron depressing synapses for neuronal synchrony detection. IJCNN Takahide Oya, Tetsuya Asai, Ryo Kagaya, Yoshihito Amemiya
2005	J	`jnl`	On the fault tolerance of a clustered single-electron neural network for differential enhancement. IEICE Electron. Express Takahide Oya, Alexandre Schmid, Tetsuya Asai, Yusuf Leblebici, Yoshihito Amemiya
2005	J	`jnl`	Reaction-Diffusion Systems Consisting of Single-Electron Oscillators. Int. J. Unconv. Comput. Takahide Oya, Tetsuya Asai, Takashi Fukui, Yoshihito Amemiya
2005	—	`book`	Reaction-diffusion computers. Andrew Adamatzky, Ben de Lacy Costello, Tetsuya Asai
2005	J	`jnl`	Silicon Implementation of a Chemical Reaction-diffusion Processor for Computation of Voronoi Diagram. Int. J. Bifurc. Chaos Tetsuya Asai, Ben de Lacy Costello, Andrew Adamatzky
2005	—	`conf`	Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. ISCAS (3) Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici
2005	J	`jnl`	Ultralow-Power Current Reference Circuit with Low Temperature Dependence. IEICE Trans. Electron. Tetsuya Hirose, Toshimasa Matsuoka, Kenji Taniguchi, Tetsuya Asai, Yoshihito Amemiya
2004	J	`jnl`	A MOS circuit for bursting neural oscillators with excitable oregonators. IEICE Electron. Express Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2004	B	`conf`	A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection. IJCNN Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya
2004	J	`jnl`	A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection. Int. J. Robotics Autom. Yusuke Kanazawa, Tetsuya Asai, Masayuki Ikebe, Yoshihito Amemiya
2004	—	`conf`	An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots. ISCAS (3) Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2004	J	`jnl`	Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller. J. Robotics Mechatronics Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2004	J	`jnl`	Design of an Artificial Central Pattern Generator with Feedback Controller. Intell. Autom. Soft Comput. Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2004	J	`jnl`	Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. IEICE Electron. Express Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2003	J	`jnl`	A subthreshold MOS neuron circuit based on the Volterra system. IEEE Trans. Neural Networks Tetsuya Asai, Yusuke Kanazawa, Yoshihito Amemiya
2003	J	`jnl`	An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion. IEEE Trans. Neural Networks Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2003	B	`conf`	An analog neural oscillator circuit for locomotion controller in quadruped walking robot. IJCNN Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2003	J	`jnl`	Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses. J. Robotics Mechatronics Yusuke Kanazawa, Tetsuya Asai, Yoshihito Amemiya
2003	—	`conf`	Biomorphic Analog Devices based on Reaction-Diffusion Systems. ISMVL Tetsuya Asai, Yoshihito Amemiya
2002	J	`jnl`	A CMOS Reaction-Diffusion Circuit Based on Cellular-Automaton Processing Emulating the Belousov-Zhabotinsky Reaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tetsuya Asai, Yuusaku Nishimiya, Yoshihito Amemiya
2002	B	`conf`	A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology. SMC Yusuke Kanazawa, Takashi Yamada, Tetsuya Asai, Yoshihito Amemiya
2000	—	`conf`	An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks. IJCNN (3) Tetsuya Asai, Masato Koutani, Yoshihito Amemiya
2000	J	`jnl`	Simultaneous parametric uncertainty modeling and robust control synthesis by LFT scaling. Autom. Tetsuya Asai, Shinji Hara, Tetsuya Iwasaki
1999	J	`jnl`	A subthreshold MOS circuit for the Lotka-Volterra neural network producing the winners-share-all solution. Neural Networks Tetsuya Asai, Tomoki Fukai, Shigeru Tanaka
1999	J	`jnl`	Analog integrated circuits for the Lotka-Volterra competitive neural networks. IEEE Trans. Neural Networks Tetsuya Asai, Masashiro Ohtani, Hiroo Yonezu
1998	—	`conf`	An analog integrated circuit for motion detection. KES (3) Hiroo Yonezu, Tetsuya Asai, Masahiro Ohtani, Jang-Kyoo Shin, Naoki Ohshima
1996	J	`jnl`	A MOS circuit for a nonmonotonic neural network with excellent retrieval capabilities. IEEE Trans. Neural Networks Tetsuya Asai, Hideyo Yokotsuka, Tomoki Fukai