Tetsushi Koide

107 papers A 1B 4C 16Misc 2Journal 39Unranked 45

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	An Automatic Segmentation Method for Lesion Areas in Full-screen NBI Colorectal Endoscopy Using Deep Learning. IEICE Trans. Inf. Syst. Yongfei Wu, Daisuke Katayama, Tetsushi Koide, Toru Tamaki, Shigeto Yoshida, Shin Morimoto, Shiro Oka, Shinji Tanaka
2022	J	`jnl`	Classification with CNN features and SVM on Embedded DSP Core for Colorectal Magnified NBI Endoscopic Video Image. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Toru Tamaki, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
2022	J	`jnl`	Feasibility Study for Computer-Aided Diagnosis System with Navigation Function of Clear Region for Real-Time Endoscopic Video Image on Customizable Embedded DSP Cores. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayuki Odagawa, Tetsushi Koide, Toru Tamaki, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
2021	J	`jnl`	A Hardware Implementation on Customizable Embedded DSP Core for Colorectal Tumor Classification with Endoscopic Video toward Real-Time Computer-Aided Diagnosais System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka, Takayuki Sugawara, Hiroshi Toishi, Masayuki Tsuji, Nobuo Tamba
2021	—	`conf`	An Image Segmentation Method for Automatic Analysis of Skin Surface Structure in Atopic Dermatitis by the Impression Mold Technique. MWSCAS Ryuichi Michida, Seiji Izakura, Tetsushi Koide, Yuki Hayashida, Yumi Aoyama
2021	—	`conf`	Sweat Droplets Detection Using Image Segmentation on Skin Surface for Evaluation of Sweating Responses to Thermal Stimulus in Atopic Dermatitis. MWSCAS Tetsushi Koide, Ryuichi Michida, Seiji Izakura, Yuki Hayashida, Yumi Aoyama
2020	—	`conf`	Acceleration of arithmetic processing with CAM-based massive-parallel SIMD matrix core. MWSCAS Kyosuke Kageyama, Kensuke Watanabe, Akimitsu Hamai, Takeshi Kumaki, Tetsushi Koide
2020	C	`conf`	Classification Method with CNN features and SVM for Computer-Aided Diagnosis System in Colorectal Magnified NBI Endoscopy. TENCON Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shinji Tanaka
2019	C	`conf`	A Hardware Implementation of Colorectal Tumor Classification for Endoscopic Video on Customizable DSP Toward Real-Time Computer-Aided Diagnosis System. ISCAS Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka, Takayuki Sugawara, Hiroshi Toishi, Masayuki Tsuji, Nobuo Tamba
2019	—	`conf`	An IoT-gateway with the information-centric communication. ISDCS Kazunari Inoue, Nozomi Kobori, Atsushi Hirota, Tetsushi Koide, Takumi Okamoto
2019	—	`conf`	Development of In-situ Monitoring System for Crop Growth Observation. ISDCS Hideki Murakami, Yoshiki Tanaka, Jun-ichi Yamashita, Rikako Takeshita, Yasunori Sakane, Takumi Okamoto, Tetsushi Koide
2019	—	`conf`	Feature Extraction of Colorectal Endoscopic Images for Computer-Aided Diagnosis with CNN. ISDCS Takumi Okamoto, Masayuki Odagawa, Tetsushi Koide, Shinji Tanaka, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shigeto Yoshida, Hiroshi Mieno
2019	—	`conf`	Low Cost and Robust Field-Deployable Environmental Sensor for Smart Agriculture. ISDCS Toshihiro Kasama, Tetsushi Koide, Wojciech P. Bula, Yukio Yaji, Yoshishige Endo, Ryo Miyake
2019	—	`conf`	Structuring Element-counting Approach for Morphological Pattern Spectrum-based Image Manipulation Detection. ISDCS Kyosuke Kageyama, Takeshi Kumaki, Tetsushi Koide
2018	C	`conf`	An Image Analysis Method for Lettuce Leaf and Root Growth Analysis in Hydroponic Culture. TENCON Takumi Okamoto, Yasunori Sakane, Tetsushi Koide, Atsushi Ogawa, Masashi Komine, Chiharu Sone, Yoshihiro Kaneta, Yukio Yaji, Kyoko Toyofuku, Takahiro Kamata, Ken Kimura, Yoko Ishikawa, Toshihiro Kasama, Wojciech-Piptr Bula, Yoshishige Endo, Ryo Miyake
2018	C	`conf`	Implementation of Computer-Aided Diagnosis System on Customizable DSP Core for Colorectal Endoscopic Images with CNN Features and SVM. TENCON Takumi Okamoto, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Hiroshi Toishi, Takayuki Sugawara, Masayuki Tsuji, Masayuki Odagawa, Nobuo Tamba, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shinji Tanaka
2016	J	`jnl`	Computer-Aided Colorectal Tumor Classification in NBI Endoscopy Using CNN Features. CoRR Toru Tamaki, Shoji Sonoyama, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
2016	J	`jnl`	Corrigendum to "Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition" [Artif. Intell. Med. 68 (March 2016) 1-16]. Artif. Intell. Medicine Tsubasa Hirakawa, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Yoko Kominami, Shinji Tanaka
2016	J	`jnl`	Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition. Artif. Intell. Medicine Tsubasa Hirakawa, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Yoko Kominami, Shinji Tanaka
2016	J	`jnl`	Development of a Real-time Colorectal Tumor Classification System for Narrow-band Imaging zoom-videoendoscopy. CoRR Tsubasa Hirakawa, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
2016	—	`conf`	Discriminative Subtree Selection for NBI Endoscopic Image Labeling. ACCV Workshops (2) Tsubasa Hirakawa, Toru Tamaki, Takio Kurita, Bisser Raytchev, Kazufumi Kaneda, Chaohui Wang, Laurent Najman, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
2016	J	`jnl`	Domain Adaptation with L2 constraints for classifying images from different endoscope systems. CoRR Toru Tamaki, Shoji Sonoyama, Takio Kurita, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka, Kazuaki Chayama
2016	J	`jnl`	Transfer Learning for Endoscopic Image Classification. CoRR Shoji Sonoyama, Toru Tamaki, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
2015	—	`conf`	Image segmentation of pyramid style identifier based on Support Vector Machine for colorectal endoscopic images. EMBC Takumi Okamoto, Tetsushi Koide, Koki Sugi, Tatsuya Shimizu, Anh-Tuan Hoang, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
2015	B	`conf`	Trade-off between speed and performance for colorectal endoscopic NBI image classification. Image Processing Shoji Sonoyama, Toru Tamaki, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka
2015	—	`conf`	Transfer learning for Bag-of-Visual words approach to NBI endoscopic image classification. EMBC Shoji Sonoyama, Tsubasa Hirakawa, Toru Tamaki, Takio Kurita, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Yoko Kominami, Shinji Tanaka
2014	C	`conf`	Compact hardware oriented number recognition algorithm for real-time speed traffic-sign recognition. ISCAS Masaharu Yamamoto, Anh-Tuan Hoang, Mutsumi Omori, Tetsushi Koide
2014	C	`conf`	FPGA implementation of feature extraction for colorectal endoscopic images with NBI magnification. ISCAS Tsubasa Mishima, Satoshi Shigemi, Anh-Tuan Hoang, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka
2014	—	`conf`	FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification. APCCAS Tetsushi Koide, Anh-Tuan Hoang, Takumi Okamoto, Satoshi Shigemi, Tsubasa Mishima, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka
2014	—	`conf`	Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor. APCCAS Takeshi Kumaki, Takeshi Fujino, Tetsushi Koide
2014	—	`conf`	Low cost hardware implementation for traffic sign detection system. APCCAS Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto
2014	C	`conf`	Pipeline scanning architecture with computation reduction for rectangle pattern matching in real-time traffic sign detection. ISCAS Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto, Mutsumi Omori
2014	—	`conf`	SVM-MRF segmentation of colorectal NBI endoscopic images. EMBC Tsubasa Hirakawa, Tom Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka
2013	—	`conf`	Labeling colorectal NBI zoom-videoendoscope image sequences with MRF and SVM. EMBC Tsubasa Hirakawa, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeta Yoshida, Yoko Kominami, Taiji Matsuo, Rie Miyaki, Shinji Tanaka
2013	C	`conf`	Power electronics education using the integrated circuit consistent education system and TCAD. FIE Keisuke Konishi, Takeshi Tanaka, Tetsushi Koide
2013	B	`conf`	Smoothing posterior probabilities with a particle filter of dirichlet distribution for stabilizing colorectal NBI endoscopy recognition. ICIP Tsubasa Hirakawa, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka
2012	J	`jnl`	A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching. IEICE Trans. Inf. Syst. Fengwei An, Tetsushi Koide, Hans Jürgen Mattausch
2012	J	`jnl`	Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping. IEEE J. Solid State Circuits Hans Jürgen Mattausch, Wataru Imafuku, Akio Kawabata, Tania Ansari, Masahiro Yasuda, Tetsushi Koide
2011	J	`jnl`	A Scalable Massively Parallel Processor for Real-Time Image Processing. IEEE J. Solid State Circuits Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
2011	J	`jnl`	An associative memory-based learning model with an efficient hardware implementation in FPGA. Expert Syst. Appl. Ali Ahmadi, Hans Jürgen Mattausch, Md. Anwarul Abedin, Mahmoud Saeidi, Tetsushi Koide
2011	—	`conf`	Real-time hybrid learning and recognition system with software-hardware cooperation. ROBIO Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide
2011	J	`jnl`	Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems. IEICE Trans. Inf. Syst. Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Masaharu Tagami, Masakatsu Ishizaki
2010	—	`conf`	A scalable massively parallel processor for real-time image processing. ISSCC Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
2010	Misc	`conf`	Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size. ICNC Tetsushi Koide, R. Kimura, T. Sugahara, K. Okazaki, Hans Jürgen Mattausch
2010	—	`conf`	Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping. ESSCIRC Hans Jürgen Mattausch, Wataru Imafuku, Tania Ansari, Akio Kawabata, Tetsushi Koide
2010	J	`jnl`	Measurement-Based Ring Oscillator Variation Analysis. IEEE Des. Test Comput. Koh Johguchi, Akihiro Kaya, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide, Norio Sadachika
2010	Misc	`conf`	Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding. ICNC Akio Kawabata, Tetsushi Koide, Hans Jürgen Mattausch
2008	J	`jnl`	Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Trans. Electron. Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007	J	`jnl`	4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Trans. Electron. Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka
2007	—	`conf`	A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. ESSCIRC Koh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide
2007	J	`jnl`	A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin. IEICE Electron. Express Koh Johguchi, Yuya Mukuda, Ken-ichi Aoyama, Hans Jürgen Mattausch, Tetsushi Koide
2007	J	`jnl`	Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Trans. Inf. Syst. Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007	C	`conf`	Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007	J	`jnl`	Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Trans. Inf. Syst. Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007	J	`jnl`	Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Shogo Sakakibara, Tetsushi Koide, Hans Jürgen Mattausch
2007	J	`jnl`	Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory. IEICE Trans. Inf. Syst. Takeshi Kumaki, Yutaka Kono, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch
2006	B	`conf`	A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA. IEEE Congress on Evolutionary Computation Ali Ahmadi, M. Arifin Ritonga, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide
2006	J	`jnl`	A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Trans. Electron. Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto
2006	—	`conf`	An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. APCCAS Takashi Morimoto, Hidekazu Adachi, Kousuke Yamaoka, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch
2006	—	`conf`	Application of Multi-ported CAM for Parallel Coding. APCCAS Takeshi Kumaki, Y. Kouno, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch
2006	J	`jnl`	Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation. IEICE Trans. Inf. Syst. Takashi Morimoto, Hidekazu Adachi, Osamu Kiriyama, Tetsushi Koide, Hans Jürgen Mattausch
2006	—	`conf`	Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. APCCAS Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Tetsushi Koide, Hans Jürgen Mattausch
2006	—	`conf`	Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. ASP-DAC Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch
2006	C	`conf`	Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. ISCAS Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch
2006	—	`conf`	Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa
2005	J	`jnl`	A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Trans. Electron. Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide
2005	J	`jnl`	A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	—	`conf`	A low-power video segmentation LSI with boundary-active-only architecture. ASP-DAC Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch
2005	B	`conf`	A parallel hardware design for parametric active contour models. AVSS Ali Ahmadi, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide
2005	—	`conf`	CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2005	J	`jnl`	Chip size and performance evaluations of shared cache for on-chip multiprocessor. Syst. Comput. Jpn. Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide
2005	—	`conf`	Design of superscalar processor with multi-bank register file. ISCAS (4) Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch
2005	J	`jnl`	Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	—	`conf`	Object tracking in video pictures based on image segmentation and pattern matching. ISCAS (4) Takashi Morimoto, Osamu Kiriyama, Yohmei Harada, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch
2004	—	`conf`	350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. ASP-DAC Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch
2004	—	`conf`	Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. ASP-DAC Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch
2004	—	`conf`	Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. ASP-DAC Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka
2004	J	`jnl`	Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation. IEICE Trans. Inf. Syst. Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch
2003	—	`conf`	A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. ASP-DAC Tetsushi Koide, Hans Jürgen Mattausch, Yuji Yano, Takayuki Gyohten, Yoshihiro Soda
2003	—	`conf`	A novel hierarchical multi-port cache. ESSCIRC Zhaomin Zhu, Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Tetsuo Hironaka
2002	J	`jnl`	A Performance-Driven Floorplanning Method with Interconnect Performance Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinya Yamasaki, Shingo Nakaya, Shin'ichi Wakabayashi, Tetsushi Koide
2002	J	`jnl`	A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. Syst. Comput. Jpn. Shigeki Takekawa, Shin'ichi Wakabayashi, Tetsushi Koide
2002	J	`jnl`	Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance. IEEE J. Solid State Circuits Hans Jürgen Mattausch, Takayuki Gyohten, Yoshihiro Soda, Tetsushi Koide
2001	J	`jnl`	Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. Syst. Comput. Jpn. Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
2001	J	`jnl`	Topological optimization with a network reliability constraint. Discret. Appl. Math. Tetsushi Koide, S. Shinmori, H. Ishii
2000	C	`conf`	An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair. ISCAS Shingo Nakaya, Tetsushi Koide, Shin'ichi Wakabayashi
2000	—	`conf`	Genetic algorithm accelerator GAA-II. ASP-DAC Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Masataka Yamane, Hajime Ueno
2000	—	`conf`	Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. ASP-DAC Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi
1999	J	`jnl`	A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. Integr. Tetsushi Koide, Shin'ichi Wakabayashi
1999	—	`conf`	An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. ASP-DAC Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta
1999	—	`conf`	Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. ASP-DAC Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
1998	—	`conf`	A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. ASP-DAC Tetsushi Koide, Shin'ichi Wakabayashi
1998	A	`conf`	Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. PPSN Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide
1997	J	`jnl`	A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. Integr. Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida
1997	—	`conf`	Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. ASP-DAC Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru
1996	J	`jnl`	A three-layer over-the-cell multi-channel router for a new cell model. Integr. Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1996	J	`jnl`	Pin assignment with global routing for VLSI building block layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1995	C	`conf`	A Verification Algorithm for Logic Circuits with Internal Variables. ISCAS Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
1995	—	`conf`	A new performance driven placement method with the Elmore delay model for row based VLSIs. ASP-DAC Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru
1995	—	`conf`	A new system partitioning method under performance and physical constraints for multi-chip modules. ASP-DAC Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1995	—	`conf`	A three-layer over-cell multi-channel routing method for a new cell model. ASP-DAC Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1995	C	`conf`	An MCM Routing Algorithm Considering Crosstalk. ISCAS Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
1994	C	`conf`	A Floorplanning Method with Topological Constraint Manipulation. ISCAS Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1994	C	`conf`	A Systolic Graph Partitioning Algorithm for VLSI Design. ISCAS Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida
1993	—	`conf`	A new global routing algorithm for over-the-cell routing in standard cell layouts. EURO-DAC Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1993	C	`conf`	Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. ISCAS Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida
1992	—	`conf`	An optimal channel pin assignment with multiple intervals for building block layout. EURO-DAC Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida