Tetsuro Itakura

67 papers B 1C 6Journal 40Unranked 20

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation. VLSI Technology and Circuits Toshiki Sugimoto, Tuan Thanh Ta, Koichi Kokubun, Satoshi Kondo, Tetsuro Itakura, Hisaaki Katagiri, Yutaka Ota, Mitsuhiro Sengoku, Honam Kwon, Keita Sasaki, Hiroshi Kubota, Kazuhiro Suzuki, Katsuyuki Kimura, Akihide Sai
2019	J	`jnl`	Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. IEEE Trans. Very Large Scale Integr. Syst. Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura
2017	—	`conf`	28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. ISSCC Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura
2016	—	`conf`	19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. ISSCC Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura
2016	—	`conf`	20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvesting. A-SSCC Yosuke Toyama, Taichi Ogawa, Takeshi Ueno, Tetsuro Itakura
2016	—	`conf`	26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS. ISSCC Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
2016	—	`conf`	6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA. ISSCC Kei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita, Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura
2016	J	`jnl`	A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS. IEEE J. Solid State Circuits Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
2016	J	`jnl`	A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Junya Matsuno, Masanori Furuta, Tetsuro Itakura, Tatsuji Matsuura, Akira Hyogo
2016	C	`conf`	A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB. ISCAS Junya Matsuno, Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii, Masanori Furuta, Tetsuro Itakura
2015	J	`jnl`	A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Furuta, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Junya Matsuno, Shigehito Saigusa, Tetsuro Itakura
2015	C	`conf`	A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors. ISCAS Yasuhiro Shinozuka, Kei Shiraishi, Masanori Furuta, Tetsuro Itakura
2014	—	`conf`	20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication. ISSCC Shigehito Saigusa, Toshiya Mitomo, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Shusuke Kawai, Tong Wang, Masanori Furuta, Kei Shiraishi, Koichiro Ban, Seiichiro Horikawa, Tomoya Tandai, Ryoko Matsuo, Takeshi Tomizawa, Hiroaki Hoshino, Junya Matsuno, Yukako Tsutsumi, Ryoichi Tachibana, Osamu Watanabe, Tetsuro Itakura
2014	C	`conf`	A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC. ISCAS Kei Shiraishi, Daisuke Kurose, Masanori Furuta, Tetsuro Itakura
2013	—	`conf`	A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier. VLSI-DAT Junya Matsuno, Masahiro Hosoya, Masanori Furuta, Tetsuro Itakura
2013	J	`jnl`	A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Furuta, Ippei Akita, Junya Matsuno, Tetsuro Itakura
2013	J	`jnl`	All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal. IEEE Trans. Circuits Syst. I Regul. Pap. Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura
2012	—	`conf`	A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS. ISSCC Akihide Sai, Yuka Kobayashi, Shigehito Saigusa, Osamu Watanabe, Tetsuro Itakura
2012	C	`conf`	All-digital background calibration for time-interleaved ADC using pseudo aliasing signal. ISCAS Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura
2011	J	`jnl`	A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique. IEEE J. Solid State Circuits Masanori Furuta, Mai Nozawa, Tetsuro Itakura
2011	—	`conf`	A 130μA wake-up receiver SoC in 0.13μm CMOS for reducing standby power of an electric appliance controlled by an infrared remote controller. ISSCC Hiroaki Ishihara, Toshiyuki Umeda, Katsuya Ohno, Shigeyasu Iwata, Fumi Moritsuka, Tetsuro Itakura, Manabu Ishibe, Keijiro Hijikata, Yasunori Maki
2011	—	`conf`	A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop. ISSCC Akihide Sai, Takafumi Yamaji, Tetsuro Itakura
2011	—	`conf`	A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS. ESSCIRC Ippei Akita, Yuta Tsubouchi, Tetsuro Itakura, Michihiko Nishigaki, Hiroshi Uemura, Hideto Furuyama, Hideki Shibata
2011	—	`conf`	A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier. A-SSCC Ippei Akita, Masanori Furuta, Junya Matsuno, Tetsuro Itakura
2011	J	`jnl`	Current-Steering Digital-to-Analog Converter With a High-PSRR Current Switch. IEEE Trans. Circuits Syst. II Express Briefs Ippei Akita, Tetsuro Itakura, Kei Shiraishi
2011	J	`jnl`	Harmonic Signal Rejection Schemes of Polyphase Downconverters. IEEE Trans. Circuits Syst. I Regul. Pap. Takafumi Yamaji, Hiroshi Tanimoto, Junya Matsuno, Tetsuro Itakura
2010	—	`conf`	A 0.06mm ISSCC Masanori Furuta, Mai Nozawa, Tetsuro Itakura
2010	J	`jnl`	A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tomohiko Ito, Tetsuro Itakura
2010	J	`jnl`	A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura
2010	J	`jnl`	Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tetsuro Itakura
2010	J	`jnl`	Phase Compensation Techniques for Low-Power Operational Amplifiers. IEICE Trans. Electron. Rui Ito, Tetsuro Itakura
2009	J	`jnl`	A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura
2008	J	`jnl`	1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura
2008	J	`jnl`	55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers. IEICE Trans. Electron. Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
2008	J	`jnl`	A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akihide Sai, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura
2008	C	`conf`	An area-efficient sampling rate converter using negative feedback technique. ISCAS Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura
2007	J	`jnl`	A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
2007	J	`jnl`	A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme. IEEE J. Solid State Circuits Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura
2007	B	`conf`	A Direct Conversion Receiver with Fast-Settling DC Offset Canceller. PIMRC Hidenori Okuni, Rui Ito, Hiroshi Yoshida, Tetsuro Itakura
2007	J	`jnl`	A Fast IEICE Trans. Electron. Osamu Watanabe, Rui Ito, Shigehito Saigusa, Tadashi Arai, Tetsuro Itakura
2007	—	`conf`	A novel quality factor tuning scheme for active-RC filters. ESSCIRC Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura
2006	J	`jnl`	55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. IEEE J. Solid State Circuits Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
2006	—	`conf`	A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. CICC Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura
2006	C	`conf`	Balanced 3-phase analog signal processing for radio communications. ISCAS Takafumi Yamaji, Tetsuro Itakura, Rui Ito, Takeshi Ueno, Hidenori Okuni
2006	J	`jnl`	Low-Power Design of 10-bit 80-MSPS Pipeline ADCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
2005	—	`conf`	55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. ESSCIRC Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
2005	J	`jnl`	A 0.9 V 1.5 mW Continuous-Time Modulator for W-CDMA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takeshi Ueno, Tetsuro Itakura
2005	—	`conf`	A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOS. CICC Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
2005	J	`jnl`	A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter. IEICE Electron. Express Tomohiko Ito, Takeshi Ueno, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura
2005	J	`jnl`	A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA. IEICE Trans. Electron. Hiroshi Yoshida, Takehiko Toyoda, Makoto Arai, Ryuichi Fujimoto, Toshiya Mitomo, Masato Ishii, Rui Ito, Tadashi Arai, Tetsuro Itakura, Hiroshi Tsurumi
2005	J	`jnl`	Phase Compensation Technique for a Low-Power Transconductor. IEICE Trans. Electron. Rui Ito, Tetsuro Itakura, Tadashi Arai
2004	J	`jnl`	A +10-dBm IIP IEEE J. Solid State Circuits Shoji Otaka, Mitsuyuki Ashida, Masato Ishii, Tetsuro Itakura
2004	J	`jnl`	Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design. IEICE Electron. Express Tomohiko Ito, Takafumi Yamaji, Daisuke Kurose, Tetsuro Itakura
2003	J	`jnl`	A 1-V 2-GHz CMOS Up-Converter Using Self-Switching Mixers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toshiyuki Umeda, Shoji Otaka, Kenji Kojima, Tetsuro Itakura
2003	J	`jnl`	A 402-output TFT-LCD driver IC with power control based on the number of colors selected. IEEE J. Solid State Circuits Tetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda
2003	J	`jnl`	A four-input beam-forming downconverter for adaptive antennas. IEEE J. Solid State Circuits Takafumi Yamaji, Daisuke Kurose, Osamu Watanabe, Shuichi Obayashi, Tetsuro Itakura
2002	J	`jnl`	A 2-GHz Down-Converter with 3-dB Bandwidth of 600 MHz Using LO Signal Suppressing Output Buffer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Osamu Watanabe, Takafumi Yamaji, Tetsuro Itakura, Ichiro Hattori
2002	—	`conf`	A 402-output TFT-LCD driver IC with power-controlling function by selecting number of colors. CICC Tetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda
2002	J	`jnl`	A Two-Gain-Stage Amplifier without an On-Chip Miller Capacitor in an LCD Driver IC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tetsuro Itakura, Hironori Minamizaki
2002	J	`jnl`	A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching. IEEE J. Solid State Circuits Takeshi Ueno, Akira Yasuda, Takafumi Yamaji, Tetsuro Itakura
2002	J	`jnl`	A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range. IEEE J. Solid State Circuits Takafumi Yamaji, Nobuo Kanou, Tetsuro Itakura
1999	—	`conf`	A 2 V CICC Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Tadashi Arai
1999	J	`jnl`	A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC. IEEE J. Solid State Circuits Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Akira Yasuda, Ryuichi Fujimoto, Tadashi Arai, Hideyuki Kokatsu
1996	J	`jnl`	A feedforward technique with frequency-dependent current mirrors for a low-voltage wideband amplifier. IEEE J. Solid State Circuits Tetsuro Itakura, Tetsuya Iida
1996	J	`jnl`	An offset-free LPF for π/4-shift QPSK signal generator. IEEE J. Solid State Circuits Hiroshi Tanimoto, Tetsuro Itakura, Takashi Ueno, Akira Yasuda, Kazuhiro Oda
1995	J	`jnl`	Principle and applications of an autocharge-compensated sample and hold circuit. IEEE J. Solid State Circuits Takeshi Shima, Tetsuro Itakura, Shigeru Yamada, Hironori Minamizaki, Takeshi Ishioka
1992	J	`jnl`	Neuro chips with on-chip back-propagation and/or Hebbian learning. IEEE J. Solid State Circuits Takeshi Shima, Tomohisa Kimura, Yukio Kamatani, Tetsuro Itakura, Yasuhiko Fujita, Tetsuya Iida