Tetsuo Hironaka

30 papers A 3B 3C 2Journal 12Unranked 10

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	Rumpfr: A Fast and Memory Leak-free Rust Binding to the GNU MPFR Library. J. Inf. Process. Tomoya Michinaka, Hideyuki Kawabata, Tetsuo Hironaka
2019	J	`jnl`	Easy-going Development of Event-Driven Applications by Iterating a Search-Select-Superpose Loop. J. Inf. Process. Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka
2019	J	`jnl`	Efficient Searching for Essential API Member Sets based on Inclusion Relation Extraction. Int. J. Networked Distributed Comput. Yushi Kondoh, Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka
2019	C	`conf`	Extracting Inclusion Graphs of API Member Sets to Improve Searchability. SERA Yushi Kondoh, Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka
2019	A	`conf`	OSAIFU: A Source Code Factorizer on Android Studio. ICSME Masahiro Hata, Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka
2019	J	`jnl`	Resolving Ambiguous Types in Haskell by Checking Uniqueness of Type Variable Assignments under Type Class Constraints. J. Inf. Process. Yuya Kono, Hideyuki Kawabata, Tetsuo Hironaka
2019	J	`jnl`	SAIFU: Supporting Program Understanding by Automatic Indexing of Functionalities in Source Code. Int. J. Networked Distributed Comput. Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka
2019	C	`conf`	Supporting Program Understanding by Automatic Indexing of Functionalities in Source Code. SERA Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka
2018	B	`conf`	Traf: A Graphical Proof Tree Viewer Cooperating with Coq Through Proof General. APLAS Hideyuki Kawabata, Yuta Tanaka, Mai Kimura, Tetsuo Hironaka
2015	J	`jnl`	Foreword. IEICE Trans. Inf. Syst. Tetsuo Hironaka
2012	J	`jnl`	A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks. IEICE Trans. Inf. Syst. Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro
2011	—	`conf`	Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip area. ISOCC Kazuya Tanigawa, Tetsuo Hironaka
2011	—	`conf`	EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture. ReConFig Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro
2010	—	`conf`	Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor. ARC Kazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka
2008	—	`conf`	Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation. FPT Kazuya Tanigawa, Tetsuo Hironaka
2008	J	`jnl`	Evaluation of low-energy and high-performance processor using variable stages pipeline technique. IET Comput. Digit. Tech. Takahiro Sasaki, Yuji Ichikawa, Tetsuo Hironaka, Toshiaki Kitamura, Toshio Kondo
2008	B	`conf`	Exploring compact design on high throughput coarse grained reconfigurable architectures. FPL Kazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka
2007	J	`jnl`	4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Trans. Electron. Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka
2006	J	`jnl`	Scheduling support hardware for multiprocessor system and its evaluations. Syst. Comput. Jpn. Takahiro Sasaki, Tetsuo Hironaka, Naoki Nishimura, Noriyoshi Yoshida
2006	—	`conf`	Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa
2005	J	`jnl`	Chip size and performance evaluations of shared cache for on-chip multiprocessor. Syst. Comput. Jpn. Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide
2005	—	`conf`	Design of superscalar processor with multi-bank register file. ISCAS (4) Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch
2004	—	`conf`	Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. ASP-DAC Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka
2003	—	`conf`	A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism. FPT Kazuya Tanigawa, Takashi Kawasaki, Tetsuo Hironaka
2003	—	`conf`	A novel hierarchical multi-port cache. ESSCIRC Zhaomin Zhu, Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Tetsuo Hironaka
2002	B	`conf`	A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model. FPL Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida
2000	J	`jnl`	Performance Improvements of Thakore's Algorithm with Speculative Execution Technique and Dynamic Task Scheduling. Informatica (Slovenia) Takahiro Sasaki, Tetsuo Hironaka, Seiji Fujino
2000	—	`conf`	Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor system. ASP-DAC Naoki Nishimura, Takahiro Sasaki, Tetsuo Hironaka
1993	A	`conf`	A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. International Conference on Supercomputing Takashi Hashimoto, Kazuaki J. Murakami, Tetsuo Hironaka, Hiroto Yasuura
1992	A	`conf`	Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. ICS Tetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki J. Murakami, Shinji Tomita