Tetsuo Endoh

79 papers A 1C 6Journal 58Unranked 14
YearRankTypeTitle / Venue / Authors
2025 J jnl
Hardware-Efficient Activation Circuit for Edge Computing: Shifter-Polynomial Approximation of Leaky ReLU.
IEEE Trans. Circuits Syst. Artif. Intell.
Tao Li, Ko Yoshikawa, Tetsuo Endoh
2025 J jnl
Memristor State Transition Dynamics for Energy-Efficient CiM-Driven LLMs in Industrial IoT.
IEEE Internet Things J.
Tao Li, Tetsuo Endoh
2024 J jnl
Small Area and High Throughput Error Correction Module of STT-MRAM for Object Recognition Systems.
IEEE Trans. Ind. Informatics
Li Zhang, Tao Li, Tetsuo Endoh
2023 J jnl
Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator".
IEEE Trans. Very Large Scale Integr. Syst.
Tao Li, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh
2023 J jnl
From Algorithm to Module: Adaptive and Energy-Efficient Quantization Method for Edge Artificial Intelligence in IoT Society.
IEEE Trans. Ind. Informatics
Tao Li, Yitao Ma, Tetsuo Endoh
2023 J jnl
Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator.
IEEE Trans. Very Large Scale Integr. Syst.
Tao Li, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh
2023 J jnl
Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3.
Neural Comput. Appl.
Tao Li, Yitao Ma, Tetsuo Endoh
2022 — conf
Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability.
IRPS
K. Watanabe, T. Shimada, K. Hirose, H. Shindo, D. Kobayashi, Takaho Tanigawa, Shoji Ikeda, Takamitsu Shinada, Hiroki Koike, Tetsuo Endoh, T. Makino, Takeshi Ohshima
2022 J jnl
Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT.
IEEE Trans. Ind. Informatics
Tao Li, Yitao Ma, Ko Yoshikawa, Osamu Nomura, Tetsuo Endoh
2021 J jnl
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition.
IEEE J. Solid State Circuits
Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2020 J jnl
A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate.
IEEE Access
Tao Li, Yitao Ma, Tetsuo Endoh
2020 — conf
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.
VLSI Circuits
Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2020 J jnl
FPGA Implementation of Real-Time Pedestrian Detection Using Normalization-Based Validation of Adaptive Features Clustering.
IEEE Trans. Veh. Technol.
Tao Li, Yitao Ma, Hui Shen, Tetsuo Endoh
2020 J jnl
Normalization-Based Validity Index of Adaptive K-Means Clustering for Multi-Solution Application.
IEEE Access
Tao Li, Yitao Ma, Tetsuo Endoh
2019 J jnl
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
IEEE J. Solid State Circuits
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2019 — conf
A novel memory test system with an electromagnet for STT-MRAM testing.
NVMTS
Ryo Tamura, N. Watanabe, Hiroki Koike, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Soshi Sato
2019 — conf
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.
ISSCC
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2018 — conf
Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system.
NVMTS
Ryo Tamura, I. Mori, N. Watanabe, Hiroki Koike, Tetsuo Endoh
2017 — conf
Embedded nonvolatile memory with STT-MRAMs and its application for nonvolatile brain-inspired VLSIs.
VLSI-DAT
Tetsuo Endoh
2016 J jnl
An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno
2016 J jnl
Formation mechanism of concave by dielectric breakdown on silicon carbide metal-oxide-semiconductor capacitor.
Microelectron. Reliab.
Soshi Sato, Kikuo Yamabe, Tetsuo Endoh, Masaaki Niwa
2016 J jnl
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing.
Proc. IEEE
Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno
2016 C conf
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.
ISCAS
Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2015 — conf
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.
VLSIC
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2015 J jnl
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.
IEEE J. Solid State Circuits
Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2015 C conf
Nonvolatile logic and memory devices based on spintronics.
ISCAS
Tetsuo Endoh
2014 — conf
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications.
ISSCC
Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi
2014 J jnl
A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs.
IEICE Trans. Electron.
Satoru Tanoi, Tetsuo Endoh
2014 J jnl
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross
2014 J jnl
A Novel Alternating Voltage Controlled Current Sensing Method for Suppressing Thermal Dependency.
IEICE Trans. Electron.
Kazuki Itoh, Tetsuo Endoh
2014 J jnl
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure.
IEICE Electron. Express
Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014 C conf
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.
ISCAS
Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi
2014 J jnl
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme.
IEICE Electron. Express
Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014 J jnl
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme.
IEICE Electron. Express
Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2013 J jnl
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme.
IEEE J. Solid State Circuits
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2013 J jnl
A High Performance Current Latch Sense Amplifier with Vertical MOSFET.
IEICE Trans. Electron.
Hyoungjun Na, Tetsuo Endoh
2013 C conf
An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications.
ISCAS
Yitao Ma, Tadashi Shibata, Tetsuo Endoh
2013 J jnl
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications.
IEICE Electron. Express
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2013 J jnl
Foreword.
IEICE Trans. Electron.
Tetsuo Endoh
2013 — conf
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.
ISSCC
Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2012 — conf
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.
VLSIC
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2012 — conf
A 3.14 um
VLSIC
Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2012 J jnl
A Schmitt Trigger Based SRAM with Vertical MOSFET.
IEICE Trans. Electron.
Hyoungjun Na, Tetsuo Endoh
2012 J jnl
Current Controlled MOS Current Mode Logic with Auto-Detection of Threshold Voltage Fluctuation.
IEICE Trans. Electron.
Hyoungjun Na, Tetsuo Endoh
2012 J jnl
Evaluation of Performance in Vertical 1T-DRAM and Planar 1T-DRAM.
IEICE Trans. Electron.
Yuto Norifusa, Tetsuo Endoh
2012 J jnl
FG Width Scalability of the 3-D Vertical FG NAND Using the Sidewall Control Gate (SCG).
IEICE Trans. Electron.
Moon-Sik Seo, Tetsuo Endoh
2012 C conf
High-speed simulator including accurate MTJ models for spintronics integrated circuit design.
ISCAS
Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2012 — conf
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme.
ASP-DAC
Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2012 J jnl
Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating.
IEICE Trans. Electron.
Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh
2012 J jnl
Source/Drain Engineering for High Performance Vertical MOSFET.
IEICE Trans. Electron.
Takuya Imamoto, Tetsuo Endoh
2011 — conf
A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching.
ISOCC
Yitao Ma, Tetsuo Endoh, Tadashi Shibata
2011 J jnl
Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET with 65 nm CMOS Process.
IEICE Trans. Electron.
Takuya Imamoto, Takeshi Sasaki, Tetsuo Endoh
2011 J jnl
Impact of Floating Body Type DRAM with the Vertical MOSFET.
IEICE Trans. Electron.
Yuto Norifusa, Tetsuo Endoh
2011 J jnl
Study on Collective Electron Motion in Si-Nano Dot Floating Gate MOS Capacitor.
IEICE Trans. Electron.
Masakazu Muraguchi, Yoko Sakurai, Yukihiro Takada, Shintaro Nomura, Kenji Shiraishi, Mitsuhisa Ikeda, Katsunori Makihara, Seiichi Miyazaki, Yasuteru Shigeta, Tetsuo Endoh
2011 J jnl
Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET.
IEICE Trans. Electron.
Masakazu Muraguchi, Tetsuo Endoh
2011 J jnl
Temperature Dependency of Driving Current in High-k/Metal Gate MOSFET and Its Influence on CMOS Inverter Circuit.
IEICE Trans. Electron.
Takeshi Sasaki, Takuya Imamoto, Tetsuo Endoh
2011 J jnl
The Impact of Current Controlled-MOS Current Mode Logic/Magnetic Tunnel Junction Hybrid Circuit for Stable and High-Speed Operation.
IEICE Trans. Electron.
Tetsuo Endoh, Masashi Kamiyanagi, Masakazu Muraguchi, Takuya Imamoto, Takeshi Sasaki
2011 J jnl
The Optimum Physical Targets of the 3-Dimensional Vertical FG NAND Flash Memory Cell Arrays with the Extended Sidewall Control Gate (ESCG) Structure.
IEICE Trans. Electron.
Moon-Sik Seo, Tetsuo Endoh
2011 J jnl
Verification of Stable Circuit Operation of 180 nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation.
IEICE Trans. Electron.
Masashi Kamiyanagi, Takuya Imamoto, Takeshi Sasaki, Hyoungjun Na, Tetsuo Endoh
2010 C conf
A compact and low power logic design for multi-pillar vertical MOSFETs.
ISCAS
Koji Sakui, Tetsuo Endoh
2010 J jnl
Design of 30 nm FinFETs and Double Gate MOSFETs with Halo Structure.
IEICE Trans. Electron.
Tetsuo Endoh, Koji Sakui, Yukio Yasuda
2010 J jnl
Importance of the Electronic State on the Electrode in Electron Tunneling Processes between the Electrode and the Quantum Dot.
IEICE Trans. Electron.
Masakazu Muraguchi, Yukihiro Takada, Shintaro Nomura, Tetsuo Endoh, Kenji Shiraishi
2010 J jnl
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits.
IEICE Trans. Electron.
Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2010 J jnl
Study on Quantum Electro-Dynamics in Vertical MOSFET.
IEICE Trans. Electron.
Masakazu Muraguchi, Tetsuo Endoh
2010 J jnl
Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET.
IEICE Trans. Electron.
Tetsuo Endoh, Koji Sakui, Yukio Yasuda
2010 J jnl
Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit.
IEICE Trans. Electron.
Masashi Kamiyanagi, Fumitaka Iga, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2009 A conf
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues.
DATE
Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2009 J jnl
Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML Type Latch.
IEICE Trans. Electron.
Tetsuo Endoh, Masashi Kamiyanagi
2009 J jnl
Scalability of Vertical MOSFETs in Sub-10 nm Generation and Its Mechanism.
IEICE Trans. Electron.
Tetsuo Endoh, Yuto Norifusa
2009 J jnl
Study of Self-Heating Phenomena in Si Nano Wire MOS Transistor.
IEICE Trans. Electron.
Tetsuo Endoh, Yuto Norifusa
2007 J jnl
Physical Origin of Stress-Induced Leakage Currents in Ultra-Thin Silicon Dioxide Films.
IEICE Trans. Electron.
Tetsuo Endoh, Kazuyuki Hirose, Kenji Shiraishi
2007 J jnl
Study of 30-nm Double-Gate MOSFET with Halo Implantation Technology Using a Two-Dimensional Device Simulator.
IEICE Trans. Electron.
Tetsuo Endoh, Yuto Momma
2001 J jnl
0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation.
IEEE J. Solid State Circuits
Akira Tanabe, Masato Umetani, Ikuo Fujiwara, Takayuki Ogura, Kotaro Kataoka, Masao Okihara, Hiroshi Sakuraba, Tetsuo Endoh, Fujio Masuoka
2001 J jnl
An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current.
IEEE J. Solid State Circuits
Tetsuo Endoh, Kazuhisa Sunaga, Hiroshi Sakuraba, Fujio Masuoka
2001 — conf
An on-chip 96.5% current efficiency CMOS linear regulator.
ASP-DAC
Kazuhisa Sunaga, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka
1999 J jnl
New three-dimensional memory array architecture for future ultrahigh-density DRAM.
IEEE J. Solid State Circuits
Tetsuo Endoh, Katsuhisa Shinmei, Hiroshi Sakuraba, Fujio Masuoka
1993 J jnl
Reliability issues of flash memory cells.
Proc. IEEE
Seiichi Aritome, Riichiro Shirota, Gertjan Hemink, Tetsuo Endoh, Fujio Masuoka
1990 J jnl
A high-density NAND EEPROM with block-page programming for microcomputer applications.
IEEE J. Solid State Circuits
Yoshihisa Iwata, Masaki Momodomi, Tomoharu Tanaka, Hideko Oodaira, Yasuo Itoh, Ryozo Nakayama, Ryouhei Kirisawa, Seiichi Aritome, Tetsuo Endoh, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka
1989 J jnl
An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell.
IEEE J. Solid State Circuits
Masaki Momodomi, Yasuo Itoh, Riichiro Shirota, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Seiichi Aritome, Tetsuo Endoh, Kazunori Ohuchi, Fujjo Masuoka