Tetsufumi Tanamoto

18 papers A 1C 1Journal 10Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
Device/Circuit Simulations of Silicon Spin Qubits Based on a Gate-All-Around Transistor.
IEEE Access
Tetsufumi Tanamoto, Keiji Ono
2024 — conf
3D Stacked Spin Qubit by TCAD Simulations.
3DIC
Tetsufumi Tanamoto
2020 J jnl
SPICE simulation of 32-kHz crystal-oscillator operation based on Si tunnel FET.
IEICE Electron. Express
Tetsufumi Tanamoto, Chika Tanaka, Shinichi Takagi
2018 J jnl
SPICE simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation.
IEICE Electron. Express
Tetsufumi Tanamoto, Chika Tanaka, Satoshi Takaya, Masato Koyama
2017 J jnl
Physically Unclonable Function Using an Initial Waveform of Ring Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs
Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita
2017 J jnl
Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology.
CoRR
Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani
2017 J jnl
SPICE Simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation.
CoRR
Tetsufumi Tanamoto, Chika Tanaka, Satoshi Takaya, Masato Koyama
2016 J jnl
High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code.
CoRR
Tetsufumi Tanamoto, Naoharu Shimomura, Sumio Ikegawa, Mari Matsumoto, Shinobu Fujita, Hiroaki Yoda
2016 J jnl
Physically Unclonable Function using Initial Waveform of Ring Oscillators.
CoRR
Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita
2014 — conf
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU.
VLSIC
Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita
2011 J jnl
Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET
CoRR
Tetsufumi Tanamoto, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Kazutaka Ikegami, Yoshiaki Saito
2010 A conf
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only).
FPGA
Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita
2009 C conf
Perspectives and Issues in 3D-IC from Designers' Point of View.
ISCAS
Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto
2008 — conf
1200μm
ISSCC
Mari Matsumoto, Shinichi Yasuda, Ryuji Ohba, Kazutaka Ikegami, Tetsufumi Tanamoto, Shinobu Fujita
2006 — conf
3D Nanowire-Based Programmable Logic.
Nano-Net
Benjamin Gojman, Raphael Rubin, Concetta Pilotto, André DeHon, Tetsufumi Tanamoto
2006 — conf
Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation.
ISVLSI
Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita
2005 — conf
Physical random number generators for cryptographic application in mobile devices.
ESSCIRC
Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita
2004 J jnl
Physical random number generator based on MOS structure after soft breakdown.
IEEE J. Solid State Circuits
Shinichi Yasuda, Hideki Satake, Tetsufumi Tanamoto, Ryuji Ohba, Ken Uchida, Shinobu Fujita