Teruo Tanimoto

34 papers A* 4A 1B 1C 2Misc 1Journal 16Unranked 9

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Toward Ultra-High-Speed, Ultra-Low-Power Cryogenic Superconductor Computing. Computer Koji Inoue, Ilkwon Byun, Masamitsu Tanaka, Yosuke Ueno, Naoki Takeuchi, Satoshi Kawakami, Olivia Chen, Dongmoon Min, Teruo Tanimoto, Takatsugu Ono, Hiroshi Nakamura, Jangwoo Kim
2025	J	`jnl`	Approximate SFQ-Based Computing Architecture Modeling With Device-Level Guidelines. IEEE Comput. Archit. Lett. Pratiksha Mundhe, Yuta Hano, Satoshi Kawakami, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, Ilkwon Byun
2025	A*	`conf`	LSQCA: Resource-Efficient Load/Store Architecture for Limited-Scale Fault-Tolerant Quantum Computing. HPCA Takumi Kobori, Yasunari Suzuki, Yosuke Ueno, Teruo Tanimoto, Synge Todo, Yuuki Tokunaga
2025	J	`jnl`	Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays. CoRR Yasunari Suzuki, Takanori Sugiyama, Tomochika Arai, Wang Liao, Koji Inoue, Teruo Tanimoto
2024	J	`jnl`	C3-VQA: Cryogenic Counter-based Co-processor for Variational Quantum Algorithms. CoRR Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura
2024	J	`jnl`	High-Performance and Scalable Fault-Tolerant Quantum Computation with Lattice Surgery on a 2.5D Architecture. CoRR Yosuke Ueno, Taku Saito, Teruo Tanimoto, Yasunari Suzuki, Yutaka Tabuchi, Shuhei Tamate, Hiroshi Nakamura
2024	J	`jnl`	Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines. IEEE Comput. Archit. Lett. Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura
2024	J	`jnl`	LSQCA: Resource-Efficient Load/Store Architecture for Limited-Scale Fault-Tolerant Quantum Computing. CoRR Takumi Kobori, Yasunari Suzuki, Yosuke Ueno, Teruo Tanimoto, Synge Todo, Yuuki Tokunaga
2024	Misc	`conf`	Low-Power Half-Flux-Quantum based Counter Circuits for Cryogenic Quantum Computers. QCE Yuki Matsumoto, Teruo Tanimoto, Masamitsu Tanaka, Takatsugu Ono
2024	J	`jnl`	SFQ counter-based precomputation for large-scale cryogenic VQE machines. CoRR Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura
2023	—	`conf`	Circuit designs for practical-scale fault-tolerant quantum computing. VLSI Technology and Circuits Yasunari Suzuki, Yosuke Ueno, Wang Liao, Masamitsu Tanaka, Teruo Tanimoto
2023	J	`jnl`	Empirical Power-performance Analysis of Layer-wise CNN Inference on Single Board Computers. J. Inf. Process. KuanYi Ng, Aalaa M. A. Babai, Teruo Tanimoto, Satoshi Kawakami, Koji Inoue
2023	J	`jnl`	Inter-temperature Bandwidth Reduction in Cryogenic QAOA Machines. CoRR Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura
2023	—	`conf`	WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code. ASP-DAC Wang Liao, Yasunari Suzuki, Teruo Tanimoto, Yosuke Ueno, Yuuki Tokunaga
2022	—	`conf`	An Edge Autonomous Lamp Control with Camera Feedback. WF-IoT Satoshi Matsushita, Teruo Tanimoto, Satoshi Kawakami, Takatsugu Ono, Koji Inoue
2022	C	`conf`	Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device. ISCAS Iori Ishikawa, Ikki Nagaoka, Ryota Kashima, Koki Ishida, Kosuke Fukumitsu, Keitaro Oka, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Akira Fujimaki, Koji Inoue
2022	A*	`conf`	Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays. MICRO Yasunari Suzuki, Takanori Sugiyama, Tomochika Arai, Wang Liao, Koji Inoue, Teruo Tanimoto
2022	A*	`conf`	XQsim: modeling cross-technology control processors for 10+K qubit quantum computers. ISCA Ilkwon Byun, Junpyo Kim, Dongmoon Min, Ikki Nagaoka, Kosuke Fukumitsu, Iori Ishikawa, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, Jangwoo Kim
2021	J	`jnl`	Superconductor Computing for Neural Networks. IEEE Micro Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, Koji Inoue
2020	—	`conf`	32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic. VLSI Circuits Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, Koji Inoue
2020	C	`conf`	Enhancing a manycore-oriented compressed cache for GPGPU. HPC Asia Keitaro Oka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Koji Inoue
2020	—	`conf`	How Many Trials Do We Need for Reliable NISQ Computing? ISVLSI Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masao Hirokawa, Koji Inoue
2020	—	`conf`	Practical Error Modeling Toward Realistic NISQ Simulation. ISVLSI Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masao Hirokawa, Koji Inoue
2020	A*	`conf`	SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices. MICRO Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, Koji Inoue
2019	J	`jnl`	Critical Path Based Microarchitectural Bottleneck Analysis for Out-of-Order Execution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Teruo Tanimoto, Takatsugu Ono, Koji Inoue
2017	—	`conf`	CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors. CANDAR Teruo Tanimoto, Takatsugu Ono, Koji Inoue
2017	J	`jnl`	Dependence Graph Model for Accurate Critical Path Analysis on Out-of-Order Processors. J. Inf. Process. Teruo Tanimoto, Takatsugu Ono, Koji Inoue
2017	J	`jnl`	Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors. IEEE Comput. Archit. Lett. Teruo Tanimoto, Takatsugu Ono, Koji Inoue, Hiroshi Sasaki
2017	J	`jnl`	Heavy Tails in Program Structure. IEEE Comput. Archit. Lett. Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan
2017	—	`conf`	Why do programs have heavy tails? IISWC Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan
2015	J	`jnl`	A Flexible Direct Attached Storage for a Data Intensive Application. IEICE Trans. Inf. Syst. Takatsugu Ono, Yotaro Konishi, Teruo Tanimoto, Noboru Iwamatsu, Takashi Miyoshi, Jun Tanaka
2014	—	`conf`	FlexDAS: A flexible direct attached storage for I/O intensive applications. IEEE BigData Takatsugu Ono, Yotaro Konishi, Teruo Tanimoto, Noboru Iwamatsu, Takashi Miyoshi, Jun Tanaka
2014	A	`conf`	Hardware-assisted scalable flow control of shared receive queue. ICS Teruo Tanimoto, Takatsugu Ono, Kohta Nakashima, Takashi Miyoshi
2012	B	`conf`	Scalability-based manycore partitioning. PACT Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura