Terumine Hayashi

30 papers A* 1A 3B 7C 1Misc 1Journal 4Unranked 13

Year	Rank	Type	Title / Venue / Authors
2009	B	`conf`	Obstacle to training SpikeProp networks - Cause of surges in training process -. IJCNN Haruhiko Takase, Masaru Fujita, Hiroharu Kawanaka, Shinji Tsuruoka, Hidehiko Kita, Terumine Hayashi
2008	B	`conf`	Shape of error surfaces in SpikeProp. IJCNN Masaru Fujita, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi
2007	C	`conf`	Descriptive Answer Clustering System for Immediate Feedback. ICCE Kazutaka Noro, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi, Naoki Morita
2007	B	`conf`	Enhancing both generalization and fault tolerance of multilayer neural networks. IJCNN Haruhiko Takase, Masahiko Masahiko, Hidehiko Kita, Terumine Hayashi
2006	B	`conf`	Fault tolerant training algorithm for multi-layer neural networks focused on hidden unit activities. IJCNN Haruhiko Takase, Hidehiko Kita, Terumine Hayashi
2006	—	`conf`	Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing. ATS Terumine Hayashi, Naotsugu Ikeda, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita
2005	—	`conf`	A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture. Asian Test Symposium Tsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa
2005	B	`conf`	Dynamic construction of fault tolerant multi-layer neural networks. IJCNN Haruhiko Takase, Ayumi Nobuto, Hidehiko Kita, Terumine Hayashi
2005	J	`jnl`	On Test Data Compression Using Selective Don't-Care Identification. J. Comput. Sci. Technol. Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase
2004	B	`conf`	A study on the simple penalty term to the error function from the viewpoint of fault tolerant training. IJCNN Haruhiko Takase, Hidehiko Kita, Terumine Hayashi
2004	—	`conf`	Test data compression technique using selective don't-care identification. ASP-DAC Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase
2003	—	`conf`	Between-Core Vector Overlapping for Test Cost Reduction in Core Testing. Asian Test Symposium Tsuyoshi Shinogi, Yuki Yamada, Terumine Hayashi, Tomohiro Yoshikawa, Shinji Tsuruoka
2003	—	`conf`	Manipulation of hidden units activities for fault tolerant multi-layer neural networks. CIRA Yusei Katsuda, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi
2001	J	`jnl`	An enhanced fault model for high defect coverage. Syst. Comput. Jpn. Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi
2001	—	`conf`	Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems. Asian Test Symposium Tsuyoshi Shinogi, Tomokazu Kanbayashi, Tomohiro Yoshikawa, Shinji Tsuruoka, Terumine Hayashi
2000	—	`conf`	Cyclic greedy generation method for limited number of IDDQ tests. Asian Test Symposium Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi
2000	—	`conf`	Evaluation Function for Fault Tolerant Multi-Layer Neural Networks. IJCNN (3) Haruhiko Takase, Tsuyoshi Shinogi, Terumine Hayashi, Hidehiko Kita
1999	—	`conf`	A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition. ASP-DAC Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi
1999	—	`conf`	A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits. Asian Test Symposium Tsuyoshi Shinogi, Terumine Hayashi
1999	J	`jnl`	Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits. Syst. Comput. Jpn. Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki
1998	Misc	`conf`	A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Fault. VTS Tsuyoshi Shinogi, Terumine Hayashi
1998	—	`conf`	On a Logical Fault Model H1SGLF for Enhancing Defect Coverage. Asian Test Symposium Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi
1997	—	`conf`	An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits. ASP-DAC Kai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita
1997	—	`conf`	Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL. Asian Test Symposium Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki
1993	J	`jnl`	Sequential circuit test generation by real number simulation. Syst. Comput. Jpn. Kazunori Hikone, Mitsuji Ikeda, Kazumi Hatayama, Terumine Hayashi
1992	A	`conf`	Sequential Test Generation Based on Real-Value Logic. ITC Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi
1991	A	`conf`	Timing-Oriented Routers for PCB Layout Design of High-Performance Computers. ICCAD Yutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani
1990	B	`conf`	LSI module placement methods using neural computation networks. IJCNN Hiroshi Date, Mitsuho Seki, Terumine Hayashi
1989	A	`conf`	Enhanced Delay Test Generator for High-Speed Logic LSIs. ITC Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama
1986	A*	`conf`	A delay test system for high speed logic LSI's. DAC Kuniaki Kishida, F. Shirotori, Y. Ikemoto, Shun Ishiyama, Terumine Hayashi