Teruhiko Yamada

18 papers A* 1A 1Journal 11Unranked 5
YearRankTypeTitle / Venue / Authors
1999 — conf
Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset.
Asian Test Symposium
Teruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi, Koji Yamazaki
1998 J jnl
1997 Asian Test Symposium.
IEEE Des. Test Comput.
Teruhiko Yamada
1998 — conf
On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates.
Asian Test Symposium
Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa
1997 — conf
An approach to diagnose logical faults in partially observable sequential circuits.
Asian Test Symposium
Koji Yamazaki, Teruhiko Yamada
1996 — conf
On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family.
Asian Test Symposium
Teruhiko Yamada, Tsuyoshi Sasaki
1995 J jnl
A Single Bridging Fault Location Technique for CMOS Combinational Circuits.
IEICE Trans. Inf. Syst.
Koji Yamazaki, Teruhiko Yamada
1995 — conf
A simple technique for locating gate-level faults in combinational circuits.
Asian Test Symposium
Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey
1995 J jnl
Accelerating the Pace of R&D in Asia.
IEEE Des. Test Comput.
Teruhiko Yamada
1992 J jnl
A method of diagnosing single stuck-at faults in combinational circuits.
Syst. Comput. Jpn.
Teruhiko Yamada, Yoshiyuki Nakamura
1991 J jnl
Method of diagnosing multiple stuck-at-faults in combinational circuits.
Syst. Comput. Jpn.
Teruhiko Yamada, Shuji Hamada, Tatsuo Matsumoto, Toshihiko Takahashi, Takao Nakayama
1991 J jnl
Method of diagnosing single bridging faults in combinational circuit.
Syst. Comput. Jpn.
Teruhiko Yamada, Koji Yamazaki
1990 J jnl
Pseudorandom pattern built-in self-test for embedded rams.
Syst. Comput. Jpn.
Teruhiko Yamada, Hiroshi Nakajima
1988 J jnl
Test research in Japan.
IEEE Des. Test
Hideo Fujiwara, Yuzo Takamatsu, Takashi Nanya, Teruhiko Yamada, Hideo Tamamoto, Kiyoshi Furuya
1986 J jnl
Syndrome-testable design and syndrome computing method for large PLA's.
Syst. Comput. Jpn.
Teruhiko Yamada
1985 A* conf
PLAYER: a PLA design system for VLSI's.
DAC
Yoshiyuki Koseki, Teruhiko Yamada
1984 J jnl
Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults.
IEEE Trans. Computers
Teruhiko Yamada, Takashi Nanya
1983 J jnl
Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines".
IEEE Trans. Computers
Teruhiko Yamada, Takashi Nanya
1983 A conf
Syndrome-Testable Design of Programmable Logic Arrays.
ITC
Teruhiko Yamada