Terri S. Fiez - RankMe

114 papers A* 1A 3C 12Misc 2Journal 50Unranked 46

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique. IEEE J. Solid State Circuits Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Hossein Zareie, Justin B. Goins, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
2019	—	`conf`	0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique. CICC Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez
2019	—	`conf`	A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4 CICC Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
2019	J	`jnl`	A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA. IEEE Trans. Circuits Syst. II Express Briefs Hossein Mirzaie, Hamidreza Maghami, Ramin Zanbaghi, Pedram Payandehnia, Kartikeya Mayaram, Terri S. Fiez
2019	J	`jnl`	A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
2018	J	`jnl`	2017 IEEE Education Society Awards, 2017 Frontiers in Education Conference Awards, and Selected IEEE Awards. IEEE Trans. Educ. James J. Sluss, Bonnie H. Ferri, Terri S. Fiez, Joseph L. A. Hughes, Rob Reilly, Ali Mehrizi-Sani, Jeffrey E. Froyd, Justin M. Foley, Shanna Daly, Catherine Lenaway, Jamie Phillips, Yu-Tzu Lin, Cheng-Chih Wu, Ting-Yun Hou, Yu-Chih Lin, Fang-Ying Yang, Chia-Hu Chang, Hitoshi Sasaki, Takako Akakura, Gabriel Díaz, Ramon Carrasco, Beth Rieken, Mark Schar, Sheri Sheppard, Stephanie Cutler, Thomas A. Litzinger, Sarah E. Zappe, Michael Alley, Edwin C. Jones
2018	J	`jnl`	A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation. IEEE J. Solid State Circuits Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez
2018	—	`conf`	A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer. MWSCAS Hamidreza Maghami, Hossein Mirzaie, Pedram Payandehnia, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez
2017	—	`conf`	A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation. CICC Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez
2017	C	`conf`	A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC. ISCAS Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez
2016	J	`jnl`	Fast start-up analysis of resonator based oscillators using a power generation method. IET Circuits Devices Syst. Ankur Guha Roy, Kartikeya Mayaram, Terri S. Fiez
2016	—	`conf`	JetNet: A proposed protocol for reliable packet delivery in low-power IoT applications. WF-IoT Justin B. Goins, Ankur Guha Roy, Kartikeya Mayaram, Terri S. Fiez
2015	J	`jnl`	350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS. IEEE J. Solid State Circuits Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Terri S. Fiez, Kartikeya Mayaram
2015	J	`jnl`	A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator. IEEE J. Solid State Circuits Samira Zali Asl, James C. Salvia, Ginel C. Hill, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, Meghan Phadke, Shouvik Mukherjee, Haechang Lee, Charles Grosjean, Paul M. Hagelin, Sudhakar Pamarti, Terri S. Fiez, Kofi A. A. Makinwa, Aaron Partridge, Vinod Menon
2014	—	`conf`	12.9 A 1.55×0.85mm ISSCC Samira Zali Asl, Shouvik Mukherjee, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, P. Galle, Meghan Phadke, Charles Grosjean, Jim Salvia, Haechang Lee, Sudhakar Pamarti, Terri S. Fiez, Kofi A. A. Makinwa, Aaron Partridge, Vinod Menon
2014	—	`conf`	A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM. CICC Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez
2014	—	`conf`	A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networks. VLSIC Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez
2014	Misc	`conf`	Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test. VTS Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Terri S. Fiez, Mike Peng Li
2013	J	`jnl`	A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks. IEEE J. Solid State Circuits Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez
2013	J	`jnl`	An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW. IEEE J. Solid State Circuits Ramin Zanbaghi, Pavan Kumar Hanumolu, Terri S. Fiez
2012	J	`jnl`	A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
2012	—	`conf`	A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks. VLSIC Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez
2012	J	`jnl`	A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power. IEEE Trans. Circuits Syst. I Regul. Pap. Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez
2012	J	`jnl`	Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry. IEEE Trans. Very Large Scale Integr. Syst. Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez
2012	Misc	`conf`	Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques. VLSI Design Pavan Kumar Hanumolu, Un-Ku Moon, Terri S. Fiez
2011	J	`jnl`	A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS. IEEE J. Solid State Circuits Adam C. Heiberg, Thomas William Brown, Terri S. Fiez, Kartikeya Mayaram
2011	J	`jnl`	A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency. IEEE J. Solid State Circuits Thomas William Brown, Farhad Farhabakhshian, Ankur Guha Roy, Terri S. Fiez, Kartikeya Mayaram
2011	—	`conf`	A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW. CICC Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez
2011	—	`conf`	A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. CICC Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
2011	J	`jnl`	A Multiple-Input Boost Converter for Low-Power Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs Chao Shi, Brian Miller, Kartikeya Mayaram, Terri S. Fiez
2010	—	`conf`	A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/Hz. CICC Farhad Farhabakhshian, Thomas William Brown, Kartikeya Mayaram, Terri S. Fiez
2010	C	`conf`	A new zero-optimization scheme for noise-coupled ΔΣ ADCs. ISCAS Ramin Zanbaghi, Terri S. Fiez, Gabor C. Temes
2010	J	`jnl`	An Ultralow-Power Receiver for Wireless Sensor Networks. IEEE J. Solid State Circuits James Ayers, Kartikeya Mayaram, Terri S. Fiez
2009	C	`conf`	A Novel Low Power Hybrid Loop Filter for Continuous-time Sigma-delta Modulators. ISCAS Ramin Zanbaghi, Terri S. Fiez
2009	—	`conf`	Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes. ISQED Wai Leng Cheong, Brian E. Owens, Hui En Pham, Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram
2009	J	`jnl`	Frequency-Dependent Sampling Linearity. IEEE Trans. Circuits Syst. I Regul. Pap. Thomas William Brown, Mikko Hakkarainen, Terri S. Fiez
2008	—	`conf`	A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiver. CICC James Ayers, Kartikeya Mayaram, Terri S. Fiez
2008	—	`conf`	A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networks. CICC Napong Panitantum, Kartikeya Mayaram, Terri S. Fiez
2008	J	`jnl`	Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks. IEEE J. Solid State Circuits Triet Le, Kartikeya Mayaram, Terri S. Fiez
2008	J	`jnl`	Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram
2007	J	`jnl`	A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth. IEEE J. Solid State Circuits Zhimin Li, Terri S. Fiez
2007	C	`conf`	A Low Power BFSK Super-Regenerative Transceiver. ISCAS James Ayers, Kartikeya Mayaram, Terri S. Fiez
2007	—	`conf`	Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates. CICC Brett Peterson, Kartikeya Mayaram, Terri S. Fiez
2007	—	`conf`	Finding a Way: What can Computer Science Education Do? FECS Donald Heer, Carlos Jensen, Terri S. Fiez
2007	—	`conf`	Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits. CICC Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram
2007	C	`conf`	Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks. ISCAS James Ayers, Kartikeya Mayaram, Terri S. Fiez
2006	J	`jnl`	A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs. IEEE J. Solid State Circuits Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram
2006	J	`jnl`	An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
2006	—	`conf`	Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry. CICC Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez
2006	—	`conf`	Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks. CICC Triet Le, Kartikeya Mayaram, Terri S. Fiez
2006	J	`jnl`	Piezoelectric micro-power generation interface circuits. IEEE J. Solid State Circuits Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez
2006	—	`conf`	Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design Implications. CICC Thomas William Brown, Terri S. Fiez, Mikko Hakkarainen
2006	J	`jnl`	Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs. IEEE Trans. Circuits Syst. I Regul. Pap. Patrick Birrer, Sasi Kumar Arunachalam, Martin Held, Kartikeya Mayaram, Terri S. Fiez
2006	—	`conf`	Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAs. CICC Arathi Sundaresan, Terri S. Fiez, Kartikeya Mayaram
2005	A*	`conf`	A green function-based parasitic extraction method for inhomogeneous substrate layers. DAC Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram
2005	J	`jnl`	Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver. IEEE Trans. Very Large Scale Integr. Syst. Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
2005	J	`jnl`	Accurate and efficient simulation of synchronous digital switching noise in systems on a chip. IEEE Trans. Very Large Scale Integr. Syst. Husni M. Habal, Kartikeya Mayaram, Terri S. Fiez
2005	J	`jnl`	On the numerical stability of Green's function for substrate coupling in integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
2005	J	`jnl`	Simulation and measurement of supply and substrate noise in mixed-signal ICs. IEEE J. Solid State Circuits Brian E. Owens, Sirisha Adluri, Patrick Birrer, Robert Shreeve, Sasi Kumar Arunachalam, Kartikeya Mayaram, Terri S. Fiez
2004	—	`conf`	A 0.35µm current-mode T/H with -81dB THD. ISCAS (1) Madhu Chennam, Terri S. Fiez
2004	J	`jnl`	A 14-bit delta-sigma ADC with 8×OSR and 4-MHz conversion bandwidth in a 0.18-μm CMOS process. IEEE J. Solid State Circuits Ruoxin Jiang, Terri S. Fiez
2004	J	`jnl`	A comparative analysis of parallel delta-sigma ADC architectures. IEEE Trans. Circuits Syst. I Regul. Pap. Aria Eshraghi, Terri S. Fiez
2004	J	`jnl`	A noise-shaped switching power supply using a delta-sigma modulator. IEEE Trans. Circuits Syst. I Regul. Pap. Steven K. Dunlap, Terri S. Fiez
2004	—	`conf`	A physical and analytical model for substrate noise coupling analysis. ISCAS (5) Robert Shreeve, Terri S. Fiez, Kartikeya Mayaram
2004	—	`conf`	A predictive methodology for accurate substrate parasitic extraction. ISCAS (5) Ajit Sharma, Chenggang Xu, Wen Kung Chu, Nishath K. Verghese, Terri S. Fiez, Kartikeya Mayaram
2004	—	`conf`	A variable gain high linearity low power baseband filter for WLAN. ISCAS (1) Sachin Ranganathan, Terri S. Fiez
2004	—	`conf`	An accurate and efficient estimation of switching noise in synchronous digital circuits. ISCAS (2) Husni M. Habal, Terri S. Fiez, Kartikeya Mayaram
2004	J	`jnl`	An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution. IEEE Trans. Circuits Syst. I Regul. Pap. Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
2004	—	`conf`	An improved Z-parameter macro model for substrate noise coupling. ISCAS (5) Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
2004	—	`conf`	Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates. CICC Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram
2004	J	`jnl`	Process-insensitive low-power design of switched-capacitor integrators. IEEE Trans. Circuits Syst. I Regul. Pap. Ravindranath Naiknaware, Terri S. Fiez
2004	—	`conf`	Silencer!: a tool for substrate noise coupling analysis. SoCC Patrick Birrer, Terri S. Fiez, Kartikeya Mayaram
2003	J	`jnl`	A time-interleaved parallel /ΔΣ A/D converter. IEEE Trans. Circuits Syst. II Express Briefs Aria Eshraghi, Terri S. Fiez
2003	—	`conf`	Coupled Simulation of Circuit and Piezoelectric Laminates. ISQED Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
2003	J	`jnl`	Enhancing the freshman and sophomore ECE student experience using a platform for learning™. IEEE Trans. Educ. Donald Heer, Roger L. Traylor, Tom Thompson, Terri S. Fiez
2003	—	`conf`	Piezoelectric power generation interface circuits. CICC Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez
2003	—	`conf`	Strategies for simulation, measurement and suppression of digital noise in mixed-signal circuits. CICC Brian E. Owens, Patrick Birrer, Sirisha Adluri, Robert Shreeve, Sasi Kumar Arunachalam, Husni Habal, Shu-Ching Hsu, Ajit Sharma, Kartikeya Mayaram, Terri S. Fiez
2003	J	`jnl`	Using an integrated platform for learning™ to reinvent engineering education. IEEE Trans. Educ. Roger L. Traylor, Donald Heer, Terri S. Fiez
2002	J	`jnl`	A CMOS transconductor with 80-dB SFDR up to 10 MHz. IEEE J. Solid State Circuits Uma Chilakapati, Terri S. Fiez, Aria Eshraghi
2002	—	`conf`	A comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped CMOS processes. CICC Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram
2002	—	`conf`	An efficient modeling approach for substrate noise coupling analysis. ISCAS (5) Dicle Ozis, Kartikeya Mayaram, Terri S. Fiez
2002	—	`conf`	An efficient parallel delta-sigma ADC utilizing a shared multi-bit quantizer. ISCAS (3) R. Batten, Terri S. Fiez
2002	—	`conf`	Analysis of jitter in ring oscillators due to deterministic noise. ISCAS (4) Nathen Barton, Dicle Özis, Terri S. Fiez, Kartikeya Mayaram
2002	—	`conf`	Dynamic element matching in low oversampling delta sigma ADCs. ISCAS (4) Zhimin Li, Terri S. Fiez
2002	—	`conf`	The effect of supply and substrate noise on jitter in ring oscillators. CICC Nathen Barton, Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram
2001	—	`conf`	A 3.3 V transconductor in 0.35 μm CMOS with 80 dB SFDR up to 10 MHz. CICC Uma Chilakapati, Terri S. Fiez, Aria Eshraghi
2000	—	`conf`	142 dB ΔΣ ADC with a 100 nV LSB in a 3 V CMOS process. CICC Ravindranath Naiknaware, Terri S. Fiez
2000	J	`jnl`	A 14-bit current-mode ΣΔ DAC based upon rotated data weighted averaging. IEEE J. Solid State Circuits Russell E. Radke, Aria Eshraghi, Terri S. Fiez
2000	J	`jnl`	A scalable substrate noise coupling model for design of mixed-signal IC's. IEEE J. Solid State Circuits Anil Samavedam, Aline Sadate, Kartikeya Mayaram, Terri S. Fiez
1999	A	`conf`	A scalable substrate noise coupling model for mixed-signal ICs. ICCAD Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez
1999	—	`conf`	A spurious-free delta-sigma DAC using rotated data weighted averaging. CICC Russell E. Radke, Aria Eshraghi, Terri S. Fiez
1999	J	`jnl`	Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations. IEEE J. Solid State Circuits Ravindranath Naiknaware, Terri S. Fiez
1999	J	`jnl`	Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations. IEEE J. Solid State Circuits Ravindranath Naiknaware, Terri S. Fiez
1999	—	`conf`	Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes. ISCAS (6) Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez
1999	—	`conf`	Switched-capacitor integrator design optimizing for power and process variations. ISCAS (2) Ravindranath Naiknaware, Terri S. Fiez
1999	—	`conf`	Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer. ISCAS (2) Ravindranath Naiknaware, Terri S. Fiez
1998	J	`jnl`	A Nyquist-rate delta-sigma A/D converter. IEEE J. Solid State Circuits Eric T. King, Aria Eshraghi, Ian Galton, Terri S. Fiez
1998	A	`conf`	CMOS analog circuit stack generation with matching constraints. ICCAD Ravindranath Naiknaware, Terri S. Fiez
1998	—	`conf`	Schematic driven module generation for analog circuits with performance optimization and matching considerations. CICC Ravindranath Naiknaware, Terri S. Fiez
1997	A	`conf`	A low voltage CMOS current source. ISLPED Detlev Schmitt, Terri S. Fiez
1996	J	`jnl`	A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC. IEEE J. Solid State Circuits Rex T. Baird, Terri S. Fiez
1995	C	`conf`	Improved Delta-Sigma DAC Linearity Using Data Weighted Averaging. ISCAS Rex T. Baird, Terri S. Fiez
1995	C	`conf`	PWM and PCM Techniques for Control of Digitally Programmable Switching Power Supplies. ISCAS Gregory M. Cooley, Terri S. Fiez, Bryan Buchanan
1994	C	`conf`	A 12 Bit, 2V Current-Mode Pipelined A/D Converter Nonlinearity. ISCAS Ligang Zhang, Terry L. Sculley, Terri S. Fiez
1994	J	`jnl`	Accurate SI filters using RGC integrators. IEEE J. Solid State Circuits Marius Goldenberg, Russell Croman, Terri S. Fiez
1994	C	`conf`	Asynchronus Implementation for the Add Compare Select Processor for Communication Systems. ISCAS Aria Eshraghi, Terri S. Fiez, Thomas R. Fischer
1994	C	`conf`	Compact and Accurate MOST Model for Analog Circuit Hand Calculations. ISCAS Farbod Aram, Aria Eshraghi, Terri S. Fiez
1994	J	`jnl`	Design of a new squaring function for the Viterbi algorithm. IEEE J. Solid State Circuits Aria Eshraghi, Terri S. Fiez, Kel D. Winters, Thomas R. Fischer
1993	J	`jnl`	Fully balanced CMOS current-mode circuits. IEEE J. Solid State Circuits Rajesh H. Zele, David J. Allstot, Terri S. Fiez
1993	C	`conf`	Simulation of Switched-Current Systems. ISCAS Edmund M. Schneider, Terri S. Fiez
1993	C	`conf`	Stability Analysis of High-order Modulators for Delta-Sigma ADCs. ISCAS Rex T. Baird, Terri S. Fiez
1991	J	`jnl`	Switched-current circuit design issues. IEEE J. Solid State Circuits Terri S. Fiez, Guojin Liang, David J. Allstot
1990	J	`jnl`	CMOS switched-current ladder filters. IEEE J. Solid State Circuits Terri S. Fiez, David J. Allstot
1989	J	`jnl`	A family of high-swing CMOS operational amplifiers. IEEE J. Solid State Circuits Terri S. Fiez, Howard C. Yang, John J. Yang, Choung Yu, David J. Allstot