Terrence S. T. Mak

130 papers A 12B 6C 13Misc 3Journal 51Unranked 43
YearRankTypeTitle / Venue / Authors
2022 J jnl
Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon Era.
ACM J. Emerg. Technol. Comput. Syst.
Ammar Karkar, Nizar Dahir, Terrence S. T. Mak, Kin-Fai Tong
2021 J jnl
Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective.
IEEE Access
Weilong Chen, Xiaohang Wang, Ye Sun, Qiao Hu, Letian Huang, Yingtao Jiang, Amit Kumar Singh, Terrence S. T. Mak, Mei Yang
2021 J jnl
Molecular Type Spread Molecular Shift Keying for Multiple-Access Diffusive Molecular Communications.
IEEE Trans. Mol. Biol. Multi Scale Commun.
Weidong Gao, Terrence S. T. Mak, Lie-Liang Yang
2021 J jnl
On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip.
IEEE Trans. Computers
Siyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Liang Wang, Terrence S. T. Mak
2021 J jnl
Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach.
Integr.
Nizar Dahir, Ammar Karkar, Maurizio Palesi, Terrence S. T. Mak, Alex Yakovlev
2020 — conf
A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm
VLSI Circuits
Benjamin J. Fletcher, Terrence S. T. Mak, Shidhartha Das
2020 J jnl
A Fast-Transient Response Digital Low-Dropout Regulator With Dual-Modes Tuning Technique.
IEEE Trans. Circuits Syst.
Libo Qian, Da Li, Kefang Qian, Yidie Ye, Yinshui Xia, Terrence S. T. Mak
2020 J jnl
A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration.
IEEE J. Solid State Circuits
Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2020 J jnl
An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Qian Ding, Graham Knight, Terrence S. T. Mak
2020 J jnl
On hardware-trojan-assisted power budgeting system attack targeting many core systems.
J. Syst. Archit.
Yiming Zhao, Xiaohang Wang, Yingtao Jiang, Liang Wang, Mei Yang, Amit Kumar Singh, Terrence S. T. Mak
2019 C ed.
2019 Forum for Specification and Design Languages, FDL 2019, Southampton, United Kingdom, September 2-4, 2019
FDL
Tom J. Kazmierski, Reinhard von Hanxleden, Terrence S. T. Mak
2019 — conf
A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration.
ESSCIRC
Benjamin J. Fletcher, Terrence S. T. Mak, Shidhartha Das
2019 J jnl
A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liang Wang, Ping Lv, Leibo Liu, Jie Han, Ho-fung Leung, Xiaohang Wang, Shouyi Yin, Shaojun Wei, Terrence S. T. Mak
2019 A conf
A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration.
ISLPED
Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2019 J jnl
A Non-Minimal Routing Algorithm for Aging Mitigation in 2D-Mesh NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liang Wang, Xiaohang Wang, Ho-fung Leung, Terrence S. T. Mak
2019 A conf
ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip.
DATE
Siyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Terrence S. T. Mak
2019 A conf
CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs.
DATE
Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2019 J jnl
Design and Optimization of Inductive-Coupling Links for 3-D-ICs.
IEEE Trans. Very Large Scale Integr. Syst.
Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2019 J jnl
On Runtime Communication and Thermal-Aware Application Mapping and Defragmentation in 3D NoC Systems.
IEEE Trans. Parallel Distributed Syst.
Bing Li, Xiaohang Wang, Amit Kumar Singh, Terrence S. T. Mak
2019 — conf
Type-Spread Molecular Communications: Principles and Inter-Symbol Interference Mitigation.
ICC
Weidong Gao, Terrence S. T. Mak, Lie-Liang Yang
2018 J jnl
A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip.
J. Circuits Syst. Comput.
Ling Wang, Terrence S. T. Mak
2018 A conf
A high-speed design methodology for inductive coupling links in 3D-ICs.
DATE
Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2018 J jnl
A neuro-inspired visual tracking method based on programmable system-on-chip platform.
Neural Comput. Appl.
Shufan Yang, KongFatt Wong-Lin, James Andrew, Terrence S. T. Mak, T. Martin McGinnity
2018 J jnl
An integrated web-based air pollution decision support system - a prototype.
Int. J. Geogr. Inf. Sci.
Yee Leung, Kwong-Sak Leung, Man Hon Wong, Terrence S. T. Mak, Kwan-Yau Cheung, Leung-Yau Lo, Wei Ying Yi, Yuan-Lin Dong
2018 J jnl
Bubble Budgeting: Throughput Optimization for Dynamic Workloads by Exploiting Dark Cores in Many Core Systems.
IEEE Trans. Computers
Xiaohang Wang, Amit Kumar Singh, Bing Li, Yang Yang, Hong Li, Terrence S. T. Mak
2018 J jnl
Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip.
J. Syst. Archit.
Li Zhang, Xiaohang Wang, Yingtao Jiang, Mei Yang, Terrence S. T. Mak, Amit Kumar Singh
2018 C conf
Globally Wireless Locally Wired (GloWiLoW): A Clock Distribution Network for Many-Core Systems.
ISCAS
Qian Ding, Benjamin J. Fletcher, Terrence S. T. Mak
2018 A conf
Improving the efficiency of thermal covert channels in multi-/many-core systems.
DATE
Zijun Long, Xiaohang Wang, Yingtao Jiang, Guofeng Cui, Li Zhang, Terrence S. T. Mak
2018 A conf
Low-power 3D integration using inductive coupling links for neurotechnology applications.
DATE
Benjamin J. Fletcher, Shidhartha Das, Chi-Sang Poon, Terrence S. T. Mak
2018 J jnl
Network-on-Chip Multicast Architectures Using Hybrid Wire and Surface-Wave Interconnects.
IEEE Trans. Emerg. Top. Comput.
Ammar Karkar, Terrence S. T. Mak, Nizar Dahir, Ra'ed Al-Dujaily, Kin-Fai Tong, Alex Yakovlev
2018 — conf
On a New Hardware Trojan Attack on Power Budgeting of Many Core Systems.
SoCC
Yiming Zhao, Xiaohang Wang, Yingtao Jiang, Mei Yang, Amit Kumar Singh, Terrence S. T. Mak
2018 Misc conf
Special session on bringing cores closer together: The wireless revolution in on-chip communication.
VTS
Terrence S. T. Mak, Hiroki Matsutani, Partha Pratim Pande
2017 J jnl
A Resilient 2-D Waveguide Communication Fabric for Hybrid Wired-Wireless NoC Design.
IEEE Trans. Parallel Distributed Syst.
Michael Opoku Agyeman, Quoc-Tuan Vien, Ali Ahmadinia, Alexandre Yakovlev, Kin-Fai Tong, Terrence S. T. Mak
2017 J jnl
HRC: A 3D NoC Architecture with Genuine Support for Runtime Thermal-Aware Task Management.
IEEE Trans. Computers
Xiaohang Wang, Yingtao Jiang, Mei Yang, Hong Li, Terrence S. T. Mak
2017 — conf
On Runtime Communication- and Thermal-aware Application Mapping in 3D NoC.
NOCS
Bing Li, Xiaohang Wang, Amit Kumar Singh, Terrence S. T. Mak
2017 J jnl
On the Nanocommunications at THz Band in Graphene-Enabled Wireless Network-on-Chip.
CoRR
Quoc-Tuan Vien, Michael Opoku Agyeman, Tuan Anh Le, Terrence S. T. Mak
2017 C conf
Runtime task mapping for lifetime budgeting in many-core systems.
FDL
Liang Wang, Xiaohang Wang, Ho-fung Leung, Terrence S. T. Mak
2017 — conf
Throughput Optimization for Lifetime Budgeting in Many-Core Systems.
ACM Great Lakes Symposium on VLSI
Liang Wang, Xiaohang Wang, Ho-fung Leung, Terrence S. T. Mak
2016 J jnl
A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation.
IEEE Access
Ra'ed Al-Dujaily, An Li, Robert G. Maunder, Terrence S. T. Mak, Bashir M. Al-Hashimi, Lajos Hanzo
2016 J jnl
A pareto-optimal runtime power budgeting scheme for many-core systems.
Microprocess. Microsystems
Xiaohang Wang, Baoxin Zhao, Ling Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab
2016 J jnl
Adaptive Routing Algorithms for Lifetime Reliability Optimization in Network-on-Chip.
IEEE Trans. Computers
Liang Wang, Xiaohang Wang, Terrence S. T. Mak
2016 — conf
An Analytical Channel Model for Emerging Wireless Networks-on-Chip.
CSE/EUC/DCABES
Michael Opoku Agyeman, Quoc-Tuan Vien, Terrence S. T. Mak
2016 — conf
An Efficient Channel Model for Evaluating Wireless NoC Architectures.
SBAC-PAD (Workshops)
Michael Opoku Agyeman, Quoc-Tuan Vien, Gary Hill, Scott J. Turner, Terrence S. T. Mak
2016 — conf
Bubble budgeting: throughput optimization for dynamic workloads by exploiting dark cores in many core systems.
NOCS
Xiaohang Wang, Amit Kumar Singh, Bing Li, Yang Yang, Terrence S. T. Mak, Hong Li
2016 J jnl
Defragmentation for Efficient Runtime Resource Management in NoC-Based Many-Core Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Jim Ng, Xiaohang Wang, Amit Kumar Singh, Terrence S. T. Mak
2016 J jnl
IP Protection of Mesh NoCs Using Square Spiral Routing.
IEEE Trans. Very Large Scale Integr. Syst.
Qiang Liu, Wenqing Ji, Qi Chen, Terrence S. T. Mak
2016 — conf
Modular sensor system (MSS) for urban air pollution monitoring.
IEEE SENSORS
Wei-Ying Yi, Kwong-Sak Leung, Yee Leung, Helen Mei-Ling Meng, Terrence S. T. Mak
2016 J jnl
On Fine-Grained Runtime Power Budgeting for Networks-on-Chip Systems.
IEEE Trans. Computers
Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab
2016 J jnl
On runtime adaptive tile defragmentation for resource management in many-core systems.
Microprocess. Microsystems
Xiaohang Wang, Ting Fei, Boquan Zhang, Terrence S. T. Mak
2016 J jnl
Real-Time Simulation of Passage-of-Time Encoding in Cerebellum Using a Scalable FPGA-Based System.
IEEE Trans. Biomed. Circuits Syst.
Junwen Luo, Graeme Coapes, Terrence S. T. Mak, Tadashi Yamazaki, Chung Tin, Patrick Degenaar
2015 J jnl
A Survey of Wireless Sensor Network Based Air Pollution Monitoring Systems.
Sensors
Wei Ying Yi, Kin Ming Lo, Terrence S. T. Mak, Kwong-Sak Leung, Yee Leung, Helen Mei-Ling Meng
2015 — conf
An Improved Wireless Communication Fabric for Emerging Network-on-Chip Design.
FNC/MobiSPC
Michael Opoku Agyeman, Kenneth Tong, Terrence S. T. Mak
2015 J jnl
An efficient runtime power allocation scheme for many-core systems inspired from auction theory.
Integr.
Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab
2015 C conf
DeFrag: Defragmentation for Efficient Runtime Resource Allocation in NoC-Based Many-core Systems.
PDP
Jim Ng, Xiaohang Wang, Amit Kumar Singh, Terrence S. T. Mak
2015 — conf
Fine-grained runtime power budgeting for networks-on-chip.
ASP-DAC
Xiaohang Wang, Tengfei Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab
2015 J jnl
Introduction to the special issue on NoC-based many-core architectures.
Comput. Electr. Eng.
Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak
2015 A conf
Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting.
DATE
Ammar Karkar, Kin-Fai Tong, Terrence S. T. Mak, Alexandre Yakovlev
2015 — conf
Novel Hybrid Wired-Wireless Network-on-Chip Architectures: Transducer and Communication Fabric Design.
NOCS
Michael Opoku Agyeman, Wen Zong, Ji-Xiang Wan, Alex Yakovlev, Kenneth Tong, Terrence S. T. Mak
2015 — conf
On the Design of Reliable Hybrid Wired-Wireless Network-on-Chip Architectures.
MCSoC
Michael Opoku Agyeman, Ji-Xiang Wan, Quoc-Tuan Vien, Wen Zong, Alex Yakovlev, Kenneth Tong, Terrence S. T. Mak
2015 J jnl
Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Qiang Liu, Terrence S. T. Mak, Tao Zhang, Xinyu Niu, Wayne Luk, Alex Yakovlev
2015 — conf
Towards reliability and performance-aware Wireless Network-on-Chip design.
DFTS
Michael Opoku Agyeman, Kin-Fai Tong, Terrence S. T. Mak
2015 — conf
Unbiased Regional Congestion Aware Selection Function for NoCs.
NOCS
Wen Zong, Michael Opoku Agyeman, Xiaohang Wang, Terrence S. T. Mak
2014 — conf
A Novel Partitioning Algorithm for Optimizing Neuron-to-Neuron Pathways through NoC in BMI.
NoCArc@MICRO
Jim Ng, Terrence S. T. Mak
2014 — conf
A real-time silicon cerebellum spiking neural model based on FPGA.
ISIC
Junwen Luo, Graeme Coapes, Patrick Degenaar, Tadashi Yamazaki, Terrence S. T. Mak, Chung Tin
2014 — conf
A scalable FPGA-based cerebellum for passage-of-time representation.
EMBC
Junwen Luo, Graeme Coapes, Terrence S. T. Mak, Tadashi Yamazaki, Chung Tin, Patrick Degenaar
2014 A conf
Adaptive power allocation for many-core systems inspired from multiagent auction model.
DATE
Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi
2014 — conf
Agile frequency scaling for adaptive power allocation in many-core systems powered by renewable energy sources.
ASP-DAC
Xiaohang Wang, Zhiming Li, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Terrence S. T. Mak
2014 C conf
Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip.
PDP
Nizar Dahir, Ghaith Tarawneh, Terrence S. T. Mak, Ra'ed Al-Dujaily, Alex Yakovlev
2014 — conf
Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip.
VLSI-SoC (Selected Papers)
Liang Wang, Xiaohang Wang, Terrence S. T. Mak
2014 C conf
Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-Chip.
VLSI-SoC
Liang Wang, Xiaohang Wang, Terrence S. T. Mak
2014 J jnl
Eliminating Synchronization Latency Using Sequenced Latching.
IEEE Trans. Very Large Scale Integr. Syst.
Ghaith Tarawneh, Alex Yakovlev, Terrence S. T. Mak
2014 A conf
Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip.
DATE
Ammar Karkar, Nizar Dahir, Ra'ed Al-Dujaily, Kenneth Tong, Terrence S. T. Mak, Alex Yakovlev
2014 — conf
Intra- and inter-chip voltage droop analysis using a power delivery grid model.
ISIC
Wing Oi Siu, Terrence S. T. Mak
2014 J jnl
Introduction to the Special Issue on Network-on-Chip Architectures.
Comput. Electr. Eng.
Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak
2014 J jnl
Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip.
IEEE Trans. Computers
Nizar Dahir, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev
2014 J jnl
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation.
ACM Trans. Embed. Comput. Syst.
Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu, Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak
2014 J jnl
Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks.
ACM Trans. Embed. Comput. Syst.
Nizar Dahir, Ra'ed Al-Dujaily, Terrence S. T. Mak, Alex Yakovlev
2013 C conf
A Fault-Tolerant Routing Algorithm for NoC Using Farthest Reachable Routers.
DASC
Junshi Wang, Xiaohang Wang, Letian Huang, Terrence S. T. Mak, Guangjun Li
2013 — conf
A low cost, high performance dynamic-programming-based adaptive power allocation scheme for many-core architectures in the dark silicon era.
ESTIMedia
Xiaohang Wang, Zhiming Li, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Terrence S. T. Mak
2013 J jnl
Dynamic On-Chip Thermal Optimization for Three-Dimensional Networks-On-Chip.
Comput. J.
Ra'ed Al-Dujaily, Terrence S. T. Mak, Kai-Pui Lam, Fei Xia, Alex Yakovlev, Chi-Sang Poon
2013 J jnl
Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems.
ACM Trans. Design Autom. Electr. Syst.
Ra'ed Al-Dujaily, Nizar Dahir, Terrence S. T. Mak, Fei Xia, Alex Yakovlev
2013 J jnl
Efficient multicast schemes for 3-D Networks-on-Chip.
J. Syst. Archit.
Xiaohang Wang, Mei Yang, Yingtao Jiang, Maurizio Palesi, Peng Liu, Terrence S. T. Mak, Nader Bagherzadeh
2013 J jnl
Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip.
IET Comput. Digit. Tech.
Nizar Dahir, Terrence S. T. Mak, Ra'ed Al-Dujaily, Alex Yakovlev
2013 J jnl
Hybrid wire-surface wave interconnects for next-generation networks-on-chip.
IET Comput. Digit. Tech.
Ammar Karkar, Janice E. Turner, Kenneth Tong, Ra'ed Al-Dujaily, Terrence S. T. Mak, Alex Yakovlev, Fei Xia
2013 — ed.
Network on Chip Architectures, NoCArc '13, in conjunction with the 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7, 2013
NoCArc@MICRO
Maurizio Palesi, Terrence S. T. Mak, Masoud Daneshtalab
2013 — conf
Novel Multi-Layer Network Decomposition boosting acceleration of multi-core algorithms.
ASAP
Athanasios K. Grivas, Terrence S. T. Mak, Alex Yakovlev, Jonny Wray
2013 — conf
On multicast for dynamic and irregular on-chip networks using dynamic programming method.
NoCArc@MICRO
Wen Zong, Xiaohang Wang, Terrence S. T. Mak
2013 — conf
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation.
NOCS
Xiaohang Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi
2013 J jnl
On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network.
IEEE Trans. Biomed. Eng.
Bo Yu, Rosa H. M. Chan, Terrence S. T. Mak, Yihe Sun, Chi-Sang Poon
2013 C conf
Towards reliable hybrid bio-silicon integration using novel adaptive control system.
ISCAS
Junwen Luo, Patrick Degenaar, Graeme Coapes, Alex Yakovlev, Terrence S. T. Mak, Peter Andras
2012 B conf
A scalable FPGA-based design for field programmable large-scale ion channel simulations.
FPL
Graeme Coapes, Terrence S. T. Mak, Junwen Luo, Alex Yakovlev, Chi-Sang Poon
2012 — conf
Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip.
NoCArc@MICRO
Nizar Dahir, Ra'ed Al-Dujaily, Alex Yakovlev, Petros Missailidis, Terrence S. T. Mak
2012 J jnl
Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip.
IEEE Trans. Parallel Distributed Syst.
Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alex Yakovlev, Maurizio Palesi
2012 — ed.
Fifth International Workshop on Network on Chip Architectures, NoCArc '12, Vancouver, BC, Canada, December 1, 2012
NoCArc@MICRO
Maurizio Palesi, Terrence S. T. Mak
2012 B conf
Intra-chip physical parameter sensor for FPGAS using flip-flop metastability.
FPL
Ghaith Tarawneh, Terrence S. T. Mak, Alex Yakovlev
2012 — conf
Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication.
ACSD
Andrew Mundy, Terrence S. T. Mak, Alex Yakovlev, Simon Davidson, Steve B. Furber
2012 Misc conf
Minimizing power supply noise through harmonic mappings in networks-on-chip.
CODES+ISSS
Nizar Dahir, Terrence S. T. Mak, Fei Xia, Alex Yakovlev
2012 — conf
Surface wave communication system for on-chip and off-chip interconnects.
NoCArc@MICRO
Ammar Karkar, Ra'ed Al-Dujaily, Alex Yakovlev, Kenneth Tong, Terrence S. T. Mak
2012 J jnl
Truncation error analysis of MTBF computation for multi-latch synchronizers.
Microelectron. J.
Terrence S. T. Mak
2011 J jnl
Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network.
IEEE Trans. Ind. Electron.
Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk
2011 C conf
Communication centric on-chip power grid models for networks-on-chip.
VLSI-SoC
Nizar Dahir, Terrence S. T. Mak, Alex Yakovlev
2011 C conf
Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC.
VLSI-SoC
Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon
2011 C conf
Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network.
VLSI-SoC
Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon
2011 — conf
Feasibility study for future implantable neural-silicon interface devices.
EMBC
Allann Al-armaghany, Bo Yu, Terrence S. T. Mak, Kin-Fai Tong, Yihe Sun
2011 — conf
Memory efficient on-line streaming for multichannel spike train analysis.
EMBC
Bo Yu, Terrence S. T. Mak, Leslie Smith, Yihe Sun, Alex Yakovlev, Chi-Sang Poon
2011 — conf
On-chip dynamic programming networks using 3D-TSV integration.
ICSAMOS
Ra'ed Al-Dujaily, Terrence S. T. Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alexandre Yakovlev, Chi-Sang Poon
2011 — conf
Power adaptive computing system design in energy harvesting environment.
ICSAMOS
Qiang Liu, Terrence S. T. Mak, Junwen Luo, Wayne Luk, Alexandre Yakovlev
2011 J jnl
Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon
2011 — conf
Real-time neuronal networks reconstruction using hierarchical systolic arrays.
EMBC
Bo Yu, Terrence S. T. Mak, Yihe Sun, Chi-Sang Poon
2011 A conf
Redressing timing issues for speed-independent circuits in deep submicron age.
DATE
Yu Li, Terrence S. T. Mak, Alex Yakovlev
2011 — conf
Run-Time Concurrency Tuning for Peak Power Modulation in Energy Harvesting Systems.
ACSD
Yu Zhou, Terrence S. T. Mak, Alex Yakovlev
2011 A conf
Run-time deadlock detection in networks-on-chip using coupled transitive closure networks.
DATE
Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, Maurizio Palesi
2011 — conf
Towards neuro-silicon interface using reconfigurable dynamic clamping.
EMBC
Junwen Luo, Terrence S. T. Mak, Bo Yu, Peter Andras, Alex Yakovlev
2010 J jnl
A CMOS Current-Mode Dynamic Programming Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap.
Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon
2010 B conf
A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis.
FPL
Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon
2010 J jnl
Wave-pipelined intra-chip signaling for on-FPGA communications.
Integr.
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2009 Misc conf
A DP-network for optimal dynamic routing in network-on-chip.
CODES+ISSS
Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam
2009 C conf
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing.
ISCAS
Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung
2008 — conf
Global interconnections in FPGAs: modeling and performance analysis.
SLIP
Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk
2008 A conf
High-throughput interconnect wave-pipelining for global communication in FPGAs.
FPGA
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2008 — conf
Implementation of Wave-Pipelined Interconnects in FPGAs.
NOCS
Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk
2008 — conf
Interconnection lengths and delays estimation for communication links in FPGAs.
SLIP
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2008 — conf
Wave-pipelined signaling for on-FPGA communication.
FPT
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2007 C conf
A Current-Mode Analog Circuit for Reinforcement Learning Problems.
ISCAS
Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon
2007 — conf
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.
NOCS
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam
2006 B conf
On-FPGA Communication Architectures and Design Factors.
FPL
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2004 — conf
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA.
CSB
Terrence S. T. Mak, Kai-Pui Lam
2004 B conf
FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation.
FPL
Terrence S. T. Mak, Kai-Pui Lam
2004 B conf
On Computing Maximum Likelihood Phylogeny Using FPGA p.
FPL
Terrence S. T. Mak, Kai-Pui Lam
2003 — conf
High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign.
CSB
Terrence S. T. Mak, Kai-Pui Lam