Teresa Riesgo - RankMe

93 papers A 2B 8C 14Journal 32Unranked 37

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Towards an Machine Learning-Based Edge Computing Oriented Monitoring System for the Desert Border Surveillance Use Case. IEEE Access Khalifa M. Bellazi, Rodrigo Marino, José Manuel Lanza-Gutiérrez, Teresa Riesgo
2019	J	`jnl`	A Novel Data Processing Technique for Expert Resonant Nano-Pillars Transducers: A Case Study Measuring Ethanol in Water and Wine Liquid Matrices. IEEE Access Sergio Quintero, Rodrigo Marino, José Manuel Lanza-Gutiérrez, Francisco Javier Sanza, Teresa Riesgo, Miguel Holgado
2019	—	`conf`	Hardware Accelerator for Ethanol Detection in Water Media based on Machine Learning Techniques. DCIS Rodrigo Marino, Sergio Quintero, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Miguel Holgado, Jorge Portilla, Eduardo de la Torre
2018	C	`conf`	Design Space Exploration for PCA Implementation of Embedded Learning in FPGAs. ISCAS Rodrigo Marino, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Miguel Holgado
2018	J	`jnl`	Edge and Fog Computing Platform for Data Fusion of Complex Heterogeneous Sensors. Sensors Gabriel Mujica, Roberto Rodriguez-Zurrunero, Mark Richard Wilby, Jorge Portilla, Ana Belén Rodríguez-González, Álvaro Araujo, Teresa Riesgo, Juan José Vinagre-Díaz
2018	—	`conf`	Embedded Emotion Recognition within Cyber-Physical Systems using Physiological Signals. DCIS José Angel Miranda Calero, Rodrigo Marino, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Mario García-Valderas, Celia López-Ongil
2018	J	`jnl`	FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo Sensors Alfonso Rodríguez, Juan Valverde, Jorge Portilla, Andrés Otero, Teresa Riesgo, Eduardo de la Torre
2018	B	`conf`	Poster: Smart Self-Adaptive Clustering Technique for Collaborative Sensing in IoT Risk Contexts. EWSN Jaime Zornoza, Gabriel Mujica, Jorge Portilla, Teresa Riesgo
2016	J	`jnl`	A scalable H.264/AVC deblocking filter architecture. J. Real Time Image Process. Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo M. Callicó, Teresa Riesgo, Roberto Sarmiento
2016	J	`jnl`	Efficient power analysis approach and its application to system-on-chip design. Microprocess. Microsystems Yaseer Arafat Durrani, Teresa Riesgo
2016	J	`jnl`	Integrated Toolset for WSN Application Planning, Development, Commissioning and Maintenance: The WSN-DPCM ARTEMIS-JU Project. Sensors Christos P. Antonopoulos, Katerina Asimogloy, Sarah Chiti, Luca D'Onofrio, Simone Gianfranceschi, Danping He, Antonio Iodice, Stavros A. Koubias, Christos Koulamas, Luciano Lavagno, Mihai T. Lazarescu, Gabriel Mujica, George D. Papadopoulos, Jorge Portilla, Luis M. Redondo, Daniele Riccio, Teresa Riesgo, Daniel Rodríguez, Giuseppe Ruello, Vasilis Samoladas, Tsenka Stoyanova, Gerasimos Touliatos, Angela Valvo, Georgia Vlahoy
2015	C	`conf`	A novel on-site deployment, commissioning and debugging technique to assess and validate WSN based smart systems. ISCAS Gabriel Mujica, Alejandro Garcia, Javier Gordillo, Jorge Portilla, Teresa Riesgo
2015	—	`conf`	Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures. AHS Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre
2015	—	`conf`	Execution modeling in self-aware FPGA-based architectures for efficient resource management. ReCoSoC Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2015	—	`conf`	Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. ReCoSoC Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2015	J	`jnl`	Letter from the guest editors of the special issue on DCIS 2014. Microprocess. Microsystems Eduardo de la Torre, Jorge Portilla, Teresa Riesgo
2015	C	`conf`	Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform. ISCAS Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2015	J	`jnl`	Modelling and planning reliable wireless sensor networks based on multi-objective optimization genetic algorithm with changeable length. J. Heuristics Danping He, Gabriel Mujica, Jorge Portilla, Teresa Riesgo
2015	J	`jnl`	Multiple feature points representation in target localization of wireless visual sensor networks. J. Netw. Comput. Appl. Wei Li, Jorge Portilla, Félix Moreno, Guixuan Liang, Teresa Riesgo
2015	J	`jnl`	Performance evaluation of an AODV-based routing protocol implementation by using a novel in-field WSN diagnosis tool. Microprocess. Microsystems Gabriel Mujica, Jorge Portilla, Teresa Riesgo
2014	B	`conf`	A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. FPL Juan Valverde, Alfonso Rodríguez, Julio Camarero, Andrés Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2014	—	`conf`	A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor. AHS Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre, Raul Regada, Luis Berrojo
2014	J	`jnl`	Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. Microprocess. Microsystems Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2014	—	`conf`	Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration. ReCoSoC Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre, Teresa Riesgo
2014	J	`jnl`	High-Level Power Analysis for Intellectual Property-Based Digital Systems. Circuits Syst. Signal Process. Yaseer Arafat Durrani, Teresa Riesgo
2014	J	`jnl`	Power estimation for intellectual property-based digital systems at the architectural level. J. King Saud Univ. Comput. Inf. Sci. Yaseer Arafat Durrani, Teresa Riesgo
2014	—	`conf`	Power-aware multi-objective evolvable hardware system on an FPGA. AHS Blanca López, Juan Valverde, Eduardo de la Torre, Teresa Riesgo
2014	J	`jnl`	Radio propagation modeling and real test of ZigBee based indoor wireless sensor networks. J. Syst. Archit. Danping He, Gabriel Mujica, Guixuan Liang, Jorge Portilla, Teresa Riesgo
2013	C	`conf`	A 3D multi-objective optimization planning algorithm for wireless sensor networks. IECON Danping He, Jorge Portilla, Teresa Riesgo
2013	—	`conf`	A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays. IPDPS Workshops Angel Gallego, Javier Mora, Andrés Otero, Rubén Salvador, Eduardo de la Torre, Teresa Riesgo
2013	—	`conf`	A noise-agnostic self-adaptive image processing application based on evolvable hardware. DASIP Javier Mora, Angel Gallego, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo
2013	—	`conf`	A scalable evolvable hardware processing array. ReConFig Angel Gallego, Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2013	B	`conf`	A self-adaptive image processing application based on evolvable and scalable hardware. FPL Angel Gallego, Javier Mora, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo
2013	J	`jnl`	High-Level Power Analysis for Intellectual Property-Based Digital Systems. J. Low Power Electron. Yaseer Arafat Durrani, Teresa Riesgo
2013	—	`conf`	Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. DASIP Javier Mora, Angel Gallego, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2013	C	`conf`	On-the-fly dynamic reprogramming mechanism for increasing the energy efficiency and supporting multi-experimental capabilities in WSNs. IECON Gabriel Mujica, Victor Rosello, Jorge Portilla, Teresa Riesgo
2013	J	`jnl`	Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. IEEE Trans. Computers Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2012	—	`conf`	A hardware in the loop design methodology for FPGA system and its application to complex functions. VLSI-DAT Guixuan Liang, Danping He, Jorge Portilla, Teresa Riesgo
2012	J	`jnl`	Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling. Microprocess. Microsystems Rubén Salvador, Alberto Vidal, Félix Moreno, Teresa Riesgo, Lukás Sekanina
2012	—	`conf`	An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. COSADE Wei He, Eduardo de la Torre, Teresa Riesgo
2012	—	`conf`	Automatic generation of identical routing pairs for FPGA implemented DPL logic. ReConFig Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2012	—	`conf`	Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. ReConFig Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2012	C	`conf`	Hardware-software integration platform for a WSN testbed based on cookies nodes. IECON Gabriel Mujica, Victor Rosello, Jorge Portilla, Teresa Riesgo
2012	B	`conf`	Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. FPL Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2012	—	`conf`	Low-complexity timing synchronization scheme for MB-OFDM UWB receiver based on sign-bit. ICUWB Guixuan Liang, Jorge Portilla, Teresa Riesgo
2012	—	`conf`	Power management techniques in an FPGA-based WSN node for high performance applications. ReCoSoC Miguel Lombardo, Julio Camarero, Juan Valverde, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2012	C	`conf`	Simulation tool and case study for planning wireless sensor network. IECON Danping He, Gabriel Mujica, Jorge Portilla, Teresa Riesgo
2012	C	`conf`	Smart parking service based on Wireless Sensor Networks. IECON Jihoon Yang, Jorge Portilla, Teresa Riesgo
2012	J	`jnl`	Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. Sensors Juan Valverde, Andrés Otero, Miguel Lopez, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2012	J	`jnl`	Wireless Sensor Network for Environmental Monitoring: Application in a Coffee Factory. Int. J. Distributed Sens. Networks Juan Valverde, Victor Rosello, Gabriel Mujica, Jorge Portilla, Amaia Uriarte, Teresa Riesgo
2011	—	`conf`	A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. ReConFig Wei He, Eduardo de la Torre, Teresa Riesgo
2011	—	`conf`	A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. AHS Andrés Otero, Rubén Salvador, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2011	A	`conf`	A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs. ICME Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo M. Callicó, Roberto Sarmiento, Teresa Riesgo
2011	J	`jnl`	Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems. EURASIP J. Adv. Signal Process. Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina
2011	—	`conf`	Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. AHS Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2011	—	`conf`	Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. ReConFig Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo
2011	B	`conf`	Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. FPL Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastián López, Gustavo M. Callicó, Roberto Sarmiento
2010	C	`conf`	A Modular Peripheral to Support Self-Reconfiguration in SoCs. DSD Andrés Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2010	J	`jnl`	Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors. Int. J. Distributed Sens. Networks Jorge Portilla, Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Oliver Stecklina, Steffen Peter, Peter Langendörfer
2010	—	`conf`	Evolutionary design and optimization of Wavelet Transforms for image compression in embedded systems. AHS Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina
2010	—	`conf`	Generic Systolic Array for Run-Time Scalable Cores. ARC Andrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
2010	C	`conf`	High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs. DSD Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina
2010	J	`jnl`	Reconfigurable Networks on Chip: DRNoC architecture. J. Syst. Archit. Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
2010	B	`conf`	Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. FPL Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva
2009	J	`jnl`	Power estimation technique for DSP architectures. Digit. Signal Process. Yaseer Arafat Durrani, Teresa Riesgo
2009	J	`jnl`	Reconfigurable Hardware Architecture of a Shape Recognition System Based on Specialized Tiny Neural Networks With Online Training. IEEE Trans. Ind. Electron. Félix Moreno, Jaime Alarcón, Rubén Salvador, Teresa Riesgo
2008	J	`jnl`	A Binary Decision Diagram Structure for Probabilistic Switching Activity Estimation. J. Low Power Electron. Felipe Machado, Yago Torroja, Teresa Riesgo
2008	—	`conf`	A Fast Emulation-Based NoC Prototyping Framework. ReConFig Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo
2008	J	`jnl`	A Piezoelectric Minirheometer for Measuring the Viscosity of Polymer Microsamples. IEEE Trans. Ind. Electron. Almudena M. Sánchez, Roberto Prieto, Manuel Laso, Teresa Riesgo
2008	—	`conf`	Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level. PATMOS Felipe Machado, Teresa Riesgo, Yago Torroja
2007	J	`jnl`	A digital system to emulate wireless networks. IET Comput. Digit. Tech. Eduardo Peña, Eduardo de la Torre, Angel de Castro, Teresa Riesgo
2007	J	`jnl`	Architectural Power Analysis for Intellectual Property-Based Digital System. J. Low Power Electron. Yaseer Arafat Durrani, Teresa Riesgo
2007	C	`conf`	Efficient Power Macromodeling Technique for IP-Based Digital System. ISCAS Yaseer Arafat Durrani, Ana Abril, Teresa Riesgo
2007	—	`conf`	LUT-Based Power Macromodeling Technique for DSP Architectures. ICECS Yaseer Arafat Durrani, Teresa Riesgo
2007	C	`conf`	Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. ISCAS Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
2006	—	`conf`	A Hardware Library for Sensors/Actuators Interfaces in Sensor Networks. ICECS Jorge Portilla, José Luis Buron, Teresa Riesgo, Angel de Castro
2006	—	`conf`	A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits. PATMOS Felipe Machado, Teresa Riesgo, Yago Torroja
2006	J	`jnl`	A Modular Architecture for Nodes in Wireless Sensor Networks. J. Univers. Comput. Sci. Jorge Portilla, Angel de Castro, Eduardo de la Torre, Teresa Riesgo
2006	—	`conf`	Partial Reconfiguration for Core Reallocation and Flexible Communications. ReCoSoC Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
2006	—	`conf`	Power Estimation for IP-Based Modules. SoC Yaseer Arafat Durrani, Teresa Riesgo
2006	—	`conf`	Power Macromodeling for High Level Power Estimation. ReCoSoC Yaseer Arafat Durrani, Teresa Riesgo
2006	—	`conf`	Power Macromodeling for IP Modules. ICECS Yaseer Arafat Durrani, Teresa Riesgo
2006	—	`conf`	Power estimation for register transfer level by genetic algorithm. ICINCO-RA Yaseer Arafat Durrani, Teresa Riesgo, Felipe Machado
2006	J	`jnl`	Ubiquitous Computing and Ambient Intelligence: New Challenges for Computing. J. Univers. Comput. Sci. José Bravo, Xavier Alamán, Teresa Riesgo
2006	B	`conf`	Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. FPL Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly
2005	—	`conf`	Flexible Core Reallocation for Virtex II Structures. ERSA Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo
2005	C	`conf`	Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. IEEE International Workshop on Rapid System Prototyping Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo
2005	—	`conf`	Switching activity propagation of VHDL-RTL combinational designs through an automated tool. ICECS Felipe Machado, Teresa Riesgo, Yago Torroja
2004	B	`conf`	Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. FPL Mario García-Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo
2000	C	`conf`	Highly Configurable Control Boards: A Tool and a Design Experience. IEEE International Workshop on Rapid System Prototyping Eduardo de la Torre, Teresa Riesgo, Javier Uceda, E. Macip, M. Rizzi
1999	J	`jnl`	Design methodologies based on hardware description languages. IEEE Trans. Ind. Electron. Teresa Riesgo, Yago Torroja, Eduardo de la Torre
1998	A	`conf`	Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. DATE Teresa Riesgo, Yago Torroja, Eduardo de la Torre, Javier Uceda
1996	—	`conf`	A fault model for VHDL descriptions at the register transfer level. EURO-DAC Teresa Riesgo, Javier Uceda