Teresa Monreal

17 papers A* 2A 2B 1C 1Journal 8Unranked 3

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Reuse Detector: Improving the Management of STT-RAM SLLCs. CoRR Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal, José María Llabería
2023	A*	`conf`	Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs. HPCA Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Jerónimo Castrillón, Víctor Viñals
2023	—	`conf`	MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. ICECS Carlos Escuin, Fernando García-Redondo, Mahdi Zahedi, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José María Llabería, James Myers, Julien Ryckaert, Dwaipayan Biswas, Francky Catthoor
2022	J	`jnl`	Forecasting lifetime and performance of a novel NVM last-level cache with compression. CoRR Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals
2022	—	`conf`	HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches. DroneSE/RAPIDO@HiPEAC Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, Jerónimo Castrillón
2022	J	`jnl`	L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime. CoRR Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals
2021	J	`jnl`	Near-optimal replacement policies for shared caches in multicore processors. J. Supercomput. Javier Díaz, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José M. Llabería
2019	J	`jnl`	ReD: A reuse detector for content selection in exclusive shared last-level caches. J. Parallel Distributed Comput. Javier Díaz, Teresa Monreal, Pablo Ibáñez, José M. Llabería, Víctor Viñals
2009	A	`conf`	Light NUCA: A proposal for bridging the inter-cache latency gap. DATE Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals
2008	C	`conf`	Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. SBAC-PAD Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero
2007	A	`conf`	Microarchitectural Support for Speculative Register Renaming. IPDPS Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero
2006	—	`conf`	Speculative early register release. Conf. Computing Frontiers Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero
2005	J	`jnl`	Hardware support for early register release. Int. J. High Perform. Comput. Netw. Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
2004	J	`jnl`	Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero
2002	B	`conf`	Hardware Schemes for Early Register Release. ICPP Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
2000	J	`jnl`	Dynamic Register Renaming Through Virtual-Physical Registers. J. Instr. Level Parallelism Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
1999	A*	`conf`	Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals