Tejasvi Anand - RankMe

55 papers C 1Journal 25Unranked 28

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	37.4 A 100Gb/s, 1.92pJ/b Aggregate 4-Lane Single-Ended NRZ Transceiver with 15dB Far-End Crosstalk Cancellation via On-Chip Feature Extraction and Classification in 16nm FinFET. ISSCC Xiaohui Lin, Ramin Javadi, Bella Bose, Tejasvi Anand
2026	J	`jnl`	A Machine Learning-Inspired PAM-4 Transceiver for Medium-Reach Wireline Links. IEEE J. Solid State Circuits Ramin Javadi, Tejasvi Anand
2025	—	`conf`	A 0.055pJ/bit/dB 42Gb/s PAM-4 Wireline Transceiver with Consecutive Symbol to Center (CSC) Encoding and Classification for 26dB Loss in 16nm FinFET. CICC Ramin Javadi, Tejasvi Anand
2024	—	`conf`	An Enhanced Eye-Opening PAM-4 with Encoding for Short-Reach Wireline Communication Systems. MWSCAS Ramin Javadi, Tejasvi Anand
2024	J	`jnl`	An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation. IEEE J. Solid State Circuits Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand
2024	C	`conf`	Minimum Power Point Design of Inverter Based Continuous Time Linear Equalizer (CTLE). ISCAS Andrew Ensinger, Ramin Javadi, Xiaohui Lin, Bella Bose, Tejasvi Anand
2023	J	`jnl`	A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS. IEEE J. Solid State Circuits Mohamed Megahed, Tejasvi Anand
2023	—	`conf`	PLL-SAR: A New High-Speed Analog to Digital Converter Architecture. MWSCAS Vladimir Veselý, Calvin Yoji Lee, Tejasvi Anand, Un-Ku Moon
2022	J	`jnl`	A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS. IEEE J. Solid State Circuits Yusang Chun, Mohamed Megahed, Ashwin Ramachandran, Tejasvi Anand
2022	—	`conf`	A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail. VLSI Technology and Circuits Xiaohui Lin, Mohamed Megahed, Tejasvi Anand
2021	—	`conf`	A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8. VLSI Circuits Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand
2021	J	`jnl`	A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting. IEEE J. Solid State Circuits Soumya Bose, Tejasvi Anand, Matthew L. Johnston
2021	—	`conf`	A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit. VLSI Circuits Zhiping Wang, Mohamed Megahed, Yusang Chun, Tejasvi Anand
2020	J	`jnl`	A 951-fs IEEE J. Solid State Circuits Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Tejasvi Anand, Un-Ku Moon
2020	J	`jnl`	An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication - Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit. IEEE J. Solid State Circuits Yusang Chun, Tejasvi Anand
2020	J	`jnl`	An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS. IEEE J. Solid State Circuits Ashwin Ramachandran, Yusang Chun, Mohamed Megahed, Tejasvi Anand
2019	—	`conf`	A 13.6-16Gb/s Wireline Transceiver with Dicode Encoding and Sequence Detection Decoding for Equalizing 24.2dB with 2.56pJ/bit in 65nm CMOS. CICC Yusang Chun, Tejasvi Anand
2019	—	`conf`	A 3.5mV Input, 82% Peak Efficiency Boost Converter with Loss-Optimized MPPT and 50mV Integrated Cold-Start for Thermoelectric Energy Harvesting. CICC Soumya Bose, Tejasvi Anand, Matthew L. Johnston
2019	—	`conf`	A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS. ESSCIRC Yusang Chun, Ashwin Ramachandran, Tejasvi Anand
2019	—	`conf`	A Stochastic Wireline Communication System. MWSCAS Tejasvi Anand
2019	—	`conf`	A Sub 1μW Switched Source + Capacitor Architecture Free of Top/Bottom Plate Parasitic Switching Loss Achieving Peak Efficiency of 80.66% at a Regulated 1.8V Output in 180nm. CICC Mohamed Megahed, Y. Ramadass, Tejasvi Anand
2019	J	`jnl`	A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT. IEEE Trans. Circuits Syst. I Regul. Pap. Abhishekh Devaraj, Mohamed Megahed, Yutao Liu, Ashwin Ramachandran, Tejasvi Anand
2019	J	`jnl`	Integrated Cold Start of a Boost Converter at 57 mV Using Cross-Coupled Complementary Charge Pumps and Ultra-Low-Voltage Ring Oscillator. IEEE J. Solid State Circuits Soumya Bose, Tejasvi Anand, Matthew L. Johnston
2019	J	`jnl`	Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping. IEEE Trans. Circuits Syst. I Regul. Pap. Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand
2018	—	`conf`	A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOS. ISSCC Ashwin Ramachandran, Tejasvi Anand
2018	J	`jnl`	A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects. IEEE J. Solid State Circuits Da Wei, Tejasvi Anand, Guanghua Shu, José E. Schutt-Ainé, Pavan Kumar Hanumolu
2018	J	`jnl`	A Fully Decoupled LC Tank VCO Topology for Amplitude Boosted Low Phase Noise Operation. IEEE J. Solid State Circuits Bodhisatwa Sadhu, Tejasvi Anand, Scott K. Reynolds
2018	—	`conf`	Fully-integrated 57 mV cold start of a thermoelectric energy harvester using a cross-coupled complementary charge pump. CICC Soumya Bose, Tejasvi Anand, Matthew L. Johnston
2017	—	`conf`	29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS. ISSCC Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand
2017	—	`conf`	A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL. CICC Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Tejasvi Anand, Un-Ku Moon
2017	J	`jnl`	A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu
2017	J	`jnl`	A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2016	J	`jnl`	A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. IEEE J. Solid State Circuits Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu
2016	J	`jnl`	A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity. IEEE J. Solid State Circuits Tejasvi Anand, Kofi A. A. Makinwa, Pavan Kumar Hanumolu
2015	—	`conf`	10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS. ISSCC Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu
2015	—	`conf`	3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. ISSCC Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu
2015	—	`conf`	A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu
2015	J	`jnl`	A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. IEEE J. Solid State Circuits Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2015	J	`jnl`	A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links. IEEE J. Solid State Circuits Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu
2015	J	`jnl`	A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. IEEE J. Solid State Circuits Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu
2015	J	`jnl`	A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2015	—	`conf`	A self-referenced VCO-based temperature sensor with 0.034°C/mV supply sensitivity in 65nm CMOS. VLSIC Tejasvi Anand, Kofi A. A. Makinwa, Pavan Kumar Hanumolu
2015	J	`jnl`	Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers. IEEE J. Solid State Circuits Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu
2015	—	`—`	Toward realizing power scalable and energy proportional high-speed wireline links Tejasvi Anand
2014	—	`conf`	8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. ISSCC Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. VLSIC Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2014	J	`jnl`	A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links. IEEE J. Solid State Circuits Tejasvi Anand, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu
2014	—	`conf`	A 75dB DR 50MHz BW 3 VLSIC Brian Young, Karthik Reddy, Sachin Rao, Amr Elshazly, Tejasvi Anand, Pavan Kumar Hanumolu
2014	J	`jnl`	An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS. IEEE J. Solid State Circuits Mrunmay Talegaonkar, Amr Elshazly, Karthikeyan Reddy, Praveen Prabha, Tejasvi Anand, Pavan Kumar Hanumolu
2013	—	`conf`	A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time. ISSCC Tejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
2013	J	`jnl`	An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording. IEEE Trans. Very Large Scale Integr. Syst. Vikram Chaturvedi, Tejasvi Anand, Bharadwaj Amrutur
2012	—	`conf`	A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications. ICECS Kaushik Ghosal, Tejasvi Anand, Vikram Chaturvedi, Bharadwaj Amrutur
2011	—	`conf`	A scalable network port scan detection system on FPGA. FPT Tejasvi Anand, Yagnesh Waghela, Kuruvilla Varghese