Teerachot Siriburanon

74 papers C 5Journal 33Unranked 36

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	27.9 A Dual-Mode DCO-PA with a Twisted 8-Shape Inductor for BLE Achieving 42% TX Efficiency at 1.6dBm and 0.29mW RX Clock. ISSCC Jiawen Chen, Kai Xu, Luyi Guo, Teerachot Siriburanon, Jun Yin, Bashir M. Al-Hashimi, Robert Bogdan Staszewski
2026	J	`jnl`	A 24.5-45.2-GHz Low-Jitter Compact Differentially Injection-Locked Clock Multiplier With Folded-Inductor-Based Magnetic-Flux Cancellation. IEEE J. Solid State Circuits Feifan Hong, Jiawen Chen, Pingda Guan, Sayan Kumar, Robert Bogdan Staszewski, Teerachot Siriburanon
2025	—	`conf`	19.4 An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz. ISSCC Jiawen Chen, Kai Xu, Teerachot Siriburanon, Robert Bogdan Staszewski
2025	C	`conf`	A 0.012mm ISCAS Ali Esmailiyan, Teerachot Siriburanon, Dennis Andrade-Miceli, Eugene Koskin, Dirk Leipold, David J. Redmond, Imran Bashir, Elena Blokhina, Robert Bogdan Staszewski
2025	C	`conf`	A 4kb 4T eDRAM with Balanced Retention Time Adjustment. ISCAS Sayan Kumar, Dennis Andrade-Miceli, Chawin Khongprasongsiri, Teerachot Siriburanon, Robert Bogdan Staszewski
2025	J	`jnl`	A Low-Noise Digital-to-Time Converter Exploiting Waveform of Integrated Crystal Oscillator. IEEE J. Solid State Circuits Teerachot Siriburanon, Xi Chen, Chunxiao Liu, Jianglin Du, Anding Zhu, Robert Bogdan Staszewski
2025	J	`jnl`	A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations. IEEE J. Solid State Circuits Sayan Kumar, Teerachot Siriburanon, Sumit Dash, Patchara Sawakewang, Shuja Andrabi, Jon Strange, Khurram Muhammad, Chih-Ming Hung, Robert Bogdan Staszewski
2025	C	`conf`	A Ring Temperature Sensor for Quantum Applications. ISCAS Ali Esmailiyan, Eugene Koskin, Dennis Andrade-Miceli, Andrii Sokolov, Teerachot Siriburanon, Dirk Leipold, David J. Redmond, Imran Bashir, Elena Blokhina, Robert Bogdan Staszewski
2025	J	`jnl`	Analysis of Fractional Spurs in a DTC-Assisted ADPLL Exploiting Crystal-Oscillator Waveform With Harmonic-Based Digital Predistortion. IEEE Trans. Circuits Syst. II Express Briefs Chunxiao Liu, Robert Bogdan Staszewski, Teerachot Siriburanon
2025	J	`jnl`	Asymmetry Effects on Thermal and Flicker Phase Noise of Rotary Traveling-Wave Oscillators. IEEE Trans. Circuits Syst. II Express Briefs Sayan Kumar, Chawin Khongprasongsiri, Tomas Sarapas, Patchara Sawakewang, Shuja Andrabi, Jon Strange, Khurram Muhammad, Chih-Ming Hung, Teerachot Siriburanon, Robert Bogdan Staszewski
2025	C	`conf`	Trifilar-Transformer-Coupled Series-Resonance Oscillator with Enhanced Tuning Range. ISCAS Sumit Dash, Sayan Kumar, Teerachot Siriburanon, Robert Bogdan Staszewski
2024	—	`conf`	A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling. VLSI Technology and Circuits Sayan Kumar, Patchara Sawakewang, Teerachot Siriburanon, Robert Bogdan Staszewski
2024	J	`jnl`	A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces. IEEE J. Solid State Circuits Pingda Guan, Ruichang Ma, Haikun Jia, Wei Deng, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Qiuyu Peng, Teerachot Siriburanon, Robert Bogdan Staszewski, Zhihua Wang, Baoyong Chi
2024	—	`conf`	A Mixer-BBPD-Based Real-Time I/Q Calibration Loop for High-Speed Ring-Oscillators. ICTA Feifan Hong, Teerachot Siriburanon, Robert Bogdan Staszewski
2024	—	`conf`	A Tiny 3.15-43.4-GHz 3.6-mW Divide-by-8 Ring-Based Injection-Locked Frequency Divider Using Multiphase Waveform Gating Technique. A-SSCC Feifan Hong, Xi Chen, Anding Zhu, Robert Bogdan Staszewski, Teerachot Siriburanon
2024	—	`conf`	Gauging the Capability of Artificial Intelligence Chatbot Tools to Answer Textbook Coursework Exercises in Circuit Design Education. ITHET Yevhenii Mormul, Jan Przybyszewski, Teerachot Siriburanon, John Healy, Paul Cuffe
2023	J	`jnl`	A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness. IEEE J. Solid State Circuits Xi Chen, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, Anding Zhu
2023	J	`jnl`	A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications. IEEE Trans. Circuits Syst. II Express Briefs Enis Kobal, Teerachot Siriburanon, Robert Bogdan Staszewski, Anding Zhu
2023	J	`jnl`	An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS. IEEE Trans. Circuits Syst. II Express Briefs Ali Esmailiyan, Elena Blokhina, Dennis Andrade-Miceli, Eoin Faust, Panagiotis Giounanlis, Dirk Leipold, Hongying Wang, Imran Bashir, Eugene Koskin, Teerachot Siriburanon, Robert Bogdan Staszewski
2022	J	`jnl`	A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. IEEE J. Solid State Circuits Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
2022	J	`jnl`	A Compact 0.2-0.3-V Inverse-Class-F IEEE J. Solid State Circuits Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Enis Kobal, Philip Quinlan, Anding Zhu, Robert Bogdan Staszewski
2022	J	`jnl`	A G IEEE Trans. Circuits Syst. I Regul. Pap. Enis Kobal, Teerachot Siriburanon, Xi Chen, Hieu Minh Nguyen, Robert Bogdan Staszewski, Anding Zhu
2022	—	`conf`	Characterisation and Modelling of 22-nm FD-SOI Transistors Operating at Cryogenic Temperatures. ICECS 2022 Dennis Andrade-Miceli, Conor Power, Ali Esmailiyan, Teerachot Siriburanon, Imran Bashir, Mike Asker, Dirk Leipold, Robert Bogdan Staszewski, Elena Blokhina
2022	J	`jnl`	Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Xi Chen, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, Anding Zhu
2022	J	`jnl`	Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2021	—	`conf`	A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. VLSI Circuits Jianglin Du, Teerachot Siriburanon, Xi Chen, Yizhe Hu, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
2021	—	`conf`	A 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOS. ESSCIRC Enis Kobal, Teerachot Siriburanon, Robert Bogdan Staszewski, Anding Zhu
2021	J	`jnl`	A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. IEEE J. Solid State Circuits Jianglin Du, Teerachot Siriburanon, Yizhe Hu, Vivek Govindaraj, Robert Bogdan Staszewski
2021	J	`jnl`	A Type-II Phase-Tracking Receiver. IEEE J. Solid State Circuits Suoping Hu, Jianglin Du, Peng Chen, Hieu Minh Nguyen, Philip Quinlan, Teerachot Siriburanon, Robert Bogdan Staszewski
2021	J	`jnl`	Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS. IEEE Open J. Circuits Syst. Ali Esmailiyan, Jianglin Du, Teerachot Siriburanon, Filippo Schembari, Robert Bogdan Staszewski
2021	J	`jnl`	Oscillator Flicker Phase Noise: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2020	—	`conf`	17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. ISSCC Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Zhong Gao, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
2020	—	`conf`	Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process. ECCTD Pierre Bisiaux, Elena Blokhina, Eugene Koskin, Teerachot Siriburanon, Dimitri Galayko
2020	C	`conf`	Position-Based CMOS Charge Qubits for Scalable Quantum Processors at 4K. ISCAS Robert Bogdan Staszewski, Panagiotis Giounanlis, Ali Esmailiyan, Hongying Wang, Imran Bashir, Cagri Cetintepe, Dennis Andrade-Miceli, Mike Asker, Dirk Leipold, Teerachot Siriburanon, Andrii Sokolov, Elena Blokhina
2019	—	`conf`	28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications. NEWCAS Zhong Gao, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2019	—	`conf`	A 0.3V, 35% Tuning-Range, 60kHz 1/f CICC Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2019	J	`jnl`	A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. IEEE J. Solid State Circuits Hanli Liu, Atsushi Shirane, Kenichi Okada, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya
2019	—	`conf`	A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. ISSCC Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada
2019	J	`jnl`	A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS. IEEE J. Solid State Circuits Peng Chen, Feifei Zhang, Zhirui Zong, Suoping Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2019	J	`jnl`	A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. IEEE J. Solid State Circuits Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Atsushi Shirane, Kenichi Okada
2019	—	`conf`	A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip. ESSCIRC Imran Bashir, Krzysztof Pomorski, Robert Bogdan Staszewski, Mike Asker, Cagri Cetintepe, Dirk Leipold, Ali Esmailiyan, Hongying Wang, Teerachot Siriburanon, Panagiotis Giounanlis, Elena Blokhina
2019	—	`conf`	DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization. APCCAS Vivek Govindaraj, Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2019	J	`jnl`	Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators. IEEE Trans. Circuits Syst. II Express Briefs Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2018	J	`jnl`	A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS. IEEE J. Solid State Circuits Naser Pourmousavian, Feng-Wei Kuo, Teerachot Siriburanon, Masoud Babaie, Robert Bogdan Staszewski
2018	J	`jnl`	A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS. IEICE Trans. Electron. Hanli Liu, Teerachot Siriburanon, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa
2018	J	`jnl`	A Low-Flicker-Noise 30-GHz Class-F IEEE J. Solid State Circuits Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2017	—	`conf`	24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. ISSCC Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2017	J	`jnl`	64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. IEEE J. Solid State Circuits Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2017	—	`conf`	A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS. A-SSCC Peng Chen, Feifei Zhang, Zhirui Zong, Hao Zheng, Teerachot Siriburanon, Robert Bogdan Staszewski
2017	—	`conf`	A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f ESSCIRC Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2017	—	`conf`	An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ASP-DAC Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2017	—	`conf`	Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. ASICON Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. ISSCC Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shoutarou Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. IEEE J. Solid State Circuits Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. IEEE J. Solid State Circuits Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. ESSCIRC Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. ASP-DAC Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	14.1 A 0.048mm ISSCC Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. ISSCC Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. ESSCIRC Teerachot Siriburanon, Hanli Liu, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. ASP-DAC Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit. IEICE Trans. Electron. Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. IEEE J. Solid State Circuits Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	An HDL-synthesized gated-edge-injection PLL with a current output DAC. ASP-DAC Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	15.1 A 0.0066mm ISSCC Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2014	J	`jnl`	A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. IEEE J. Solid State Circuits Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. ASP-DAC Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. ASP-DAC Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A 0.022mm ISSCC Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs. ESSCIRC Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer. IEICE Trans. Electron. Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers. IEEE J. Solid State Circuits Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. ASP-DAC Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2012	—	`conf`	A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers. ESSCIRC Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa