Tay-Jyi Lin - RankMe

65 papers A 5C 12Journal 13Unranked 35

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Enhancing Semi-Supervised Learners via Similarity-Based Self-Supervised Models. NewCAS ShengPo Lin, Hsiang-Cheng Hsieh, Lianzheng Lin, Kuei-Chung Chang, Juin-Ming Lu, Tay-Jyi Lin, Tien-Fu Chen
2025	—	`conf`	Hybrid Bayesian Optimization with Early Termination Strategies for Auto Tuning. ISVLSI Hsiang-Cheng Hsieh, ShengPo Lin, Arbind Kumar Mahto, Kuei-Chung Chang, Juin-Ming Lu, Tay-Jyi Lin, Tien-Fu Chen
2024	—	`conf`	A 40-nm 13.88-TOPS/W FC-DNN Engine for 16-bit Intelligent Audio Processing Featuring Weight-Sharing and Approximate Computing. HCS Tay-Jyi Lin, Ze Li, Yun-Cheng Chen, Chien-Tung Liu, Tien-Fu Chen, Jinn-Shyan Wang
2024	—	`conf`	Efficient Inference of Transformers on Bare-Metal Devices with RISC-V Vector Processors. NewCAS Yi-Xuan Huang, Po-Han Huang, Juin-Ming Lu, Tay-Jyi Lin, Tien-Fu Chen
2024	—	`conf`	Performance Evaluation of MEMS Vibration Sensors for Throat Microphones. IEEE SENSORS Che-Yu Hsu, Po-Han Chen, Ting-Yi Chen, Shang-Yu Lin, Ching-Jen Wang, Chingwei Yeh, Tay-Jyi Lin, Pei-Zen Chang, Wei-Chang Li
2023	J	`jnl`	A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. IEEE Trans. Circuits Syst. II Express Briefs Tay-Jyi Lin, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang
2023	—	`conf`	Force-Sensing Intelligent Vise for Cutting Dynamics Monitoring in Machining. SENSORS Po-Han Chen, Tay-Jyi Lin, Chingwei Yeh, Pei-Zen Chang, Wei-Chang Li
2022	—	`conf`	A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. ASP-DAC Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang
2020	C	`conf`	A 0.21V 40nm NAND-ROM for IoT Sensing Systems with Long Standby Periods. ISCAS Jinn-Shyan Wang, Cheng-Xin Xue, Chien-Tung Liu, Tay-Jyi Lin
2018	—	`conf`	A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs. SoCC Chien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei, Jinn-Shyan Wang, Tay-Jyi Lin
2018	—	`conf`	Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications. SoCC Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Jyi Lin, Jinn-Shyan Wang
2017	—	`conf`	An all-n-type dynamic adder for ultra-low-leakage IoT devices. ASICON Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin, Jinn-Shyan Wang
2017	—	`conf`	Approximate Distributed Arithmetic for Variable-Latency Table Lookup. NGCAS Yi-Hsuan Ting, Tay-Jyi Lin, Cheng-Chun Chang, Chih-Chien Hu, Chingwei Yeh, Jinn-Shyan Wang
2017	J	`jnl`	ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. IEEE Trans. Very Large Scale Integr. Syst. Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
2016	—	`conf`	A low complexity edge-preserved image compression algorithm for LCD overdrive. GCCE Chao-Yang Chang, Chung-Hsun Huang, Hui-Fu Chen, Chingwei Yeh, Yuan-Sun Chu, Tay-Jyi Lin
2016	J	`jnl`	Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. Integr. Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
2016	—	`conf`	Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation. SoCC Yi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang, Jinn-Shyan Wang
2016	J	`jnl`	Speculative Lookahead for Energy-Efficient Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. Tay-Jyi Lin, Ting-Yu Shyu
2016	—	`conf`	Variable-length VLIW encoding for code size reduction in embedded processors. SoCC Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen
2016	J	`jnl`	Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. IEEE Trans. Circuits Syst. II Express Briefs Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
2015	—	`conf`	Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. ASICON Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang
2015	J	`jnl`	System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach. ACM Trans. Embed. Comput. Syst. Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Tay-Jyi Lin, Chih-wen Hsueh, Naehyuck Chang
2014	—	`conf`	Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET). Hot Chips Symposium Chung-Hsun Huang, Wei-Jen Chen, Keng-Jui Chang, Yi-Hsuan Ting, Keng-Chang Hsu, Yu-Fu Pan, Chao-Chun Chen, Yuan-Hua Chu, Tay-Jyi Lin, Jinn-Shyan Wang
2014	—	`conf`	Maintaining color fidelity for dual-shot HDR imaging. ICCE-TW Chingwei Yeh, Chen-Yao Tsai, Tay-Jyi Lin, Jiun-In Guo
2013	—	`conf`	A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
2013	C	`conf`	Variation-aware and adaptive-latency accesses for reliable low voltage caches. VLSI-SoC Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen
2012	J	`jnl`	A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Yen-Hsiang Yu
2012	C	`conf`	A smart stream controller for efficient implementation of streaming applications on the heterogeneous multicore processor. ISCAS Shih-Hao Ou, Che-Wei Yeh, Tay-Jyi Lin, Chih-Wei Liu
2012	—	`conf`	Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications. ASP-DAC Shyang-Chyun Chen, Chao-Chuan Chen, Wen-Chi Guo, Tay-Jyi Lin, Ching-Wei Yeh
2012	—	`conf`	Energy-efficient RISC design with on-demand circuit-level timing speculation. ASP-DAC Tay-Jyi Lin, Yu-Ting Kuo, Yu-Jung Tsai, Ting-Yu Shyu, Yuan-Hua Chu
2011	J	`jnl`	Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters. EURASIP J. Adv. Signal Process. Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu
2011	J	`jnl`	Hierarchical circuit-switched NoC for multicore video processing. Microprocess. Microsystems Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Tien-Fu Chen, Tay-Jyi Lin
2011	J	`jnl`	Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools. J. Signal Process. Syst. David Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq Kuen Lee, Yuan-Hua Chu, An-Yeu Wu
2010	—	`conf`	Collaborative voltage scaling with online STA and variable-latency datapath. ACM Great Lakes Symposium on VLSI Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu
2010	C	`conf`	Complexity-effective dynamic range compression for digital hearing aids. ISCAS Kuo-Chiang Chang, Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu
2010	J	`jnl`	Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chih-Wei Liu
2010	A	`conf`	Hierarchical memory scheduling for multimedia MPSoCs. ICCAD Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang
2010	C	`conf`	Improving energy efficiency of functional units by exploiting their data-dependent latency. ISCAS Shih-Hao Ou, Yen-Cheng Lin, Tay-Jyi Lin, Chih-Wei Liu
2010	A	`conf`	RunAssert: A non-intrusive run-time assertion for parallel programs debugging. DATE Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Tay-Jyi Lin
2009	—	`conf`	Parallel object detection on multicore platforms. SiPS Shin-Kai Chen, Tay-Jyi Lin, Chih-Wei Liu
2009	—	`conf`	Ultra low-power ANSI S1.11 filter bank for digital hearing aids. ASP-DAC Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, Chih-Wei Liu
2008	C	`conf`	Complexity-effective auditory compensation for digital hearing aids. ISCAS Yu-Ting Kuo, Tay-Jyi Lin, Wei-Han Chang, Yueh-Tai Li, Chih-Wei Liu, Shuenn-Tsong Young
2008	C	`conf`	Cycle Stealing and Channel Management for On-Chip Networks. HPCC Jwo-An Lin, Yung-Chou Tsai, Tay-Jyi Lin, Yarsun Hsu
2008	J	`jnl`	Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. J. Signal Process. Syst. Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao
2008	C	`conf`	Improving datapathutilization of programmable DSP with composite functional units. ISCAS Shih-Hao Ou, Yi Cho, Tay-Jyi Lin, Chih-Wei Liu
2008	—	`conf`	Multithreaded coprocessor interface for multi-core multimedia SoC. ASP-DAC Shih-Hao Ou, Tay-Jyi Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih-Wei Liu
2007	—	`conf`	Design of ANSI S1.11 Filter Bank for Digital Hearing Aids. ICECS Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Wei-Han Chang, Chih-Wei Liu, Shuenn-Tsong Young
2007	C	`conf`	Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. ISCAS Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
2007	C	`conf`	Rapid C to FPGA Prototyping with Multithreaded Emulation Engine. ISCAS Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu
2007	—	`conf`	Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. ASP-DAC Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu
2006	—	`conf`	A 52mW 1200MIPS compact DSP for multi-core media SoC. ASP-DAC Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
2006	J	`jnl`	A Compact DSP Core with Static Floating-Point Arithmetic. J. VLSI Signal Process. Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen
2006	C	`conf`	Programmable FIR filter with adder-based computing engine. ISCAS Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen
2005	—	`conf`	A unified processor architecture for RISC & VLIW DSP. ACM Great Lakes Symposium on VLSI Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen
2005	A	`conf`	Architecture for area-efficient 2-D transform in H.264/AVC. ICME Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
2005	—	`conf`	Hierarchical instruction encoding for VLIW digital signal processors. ISCAS (4) Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen
2005	—	`conf`	Pipelining technique for energy-aware datapaths. ISCAS (2) Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen
2004	—	`conf`	A compact DSP core with static floating-point unit & its microcode generation. ACM Great Lakes Symposium on VLSI Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
2004	—	`conf`	Static floating-point unit with implicit exponent tracking for embedded DSP. ISCAS (2) Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen
2003	C	`conf`	An Efficient VLIW DSP Architecture for Baseband Processing. ICCD Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen
2003	—	`conf`	Area-effective FIR filter design for multiplier-less implementation. ISCAS (5) Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen
2003	A	`conf`	Coefficient optimization for area-effective multiplier-less FIR filters. ICME Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen
2003	A	`conf`	Performance evaluation of ring-structure register file in multimedia applications. ICME Tay-Jyi Lin, Chin-Chi Chang, Tsung-Hsun Yang, Yu-Ming Chang, Chien-Hung Lin, Chen-Chia Lee, Hung-Yueh Lin, Chein-Wei Jen
2002	—	`conf`	CASCADE - configurable and scalable DSP environment. ISCAS (4) Tay-Jyi Lin, Chein-Wei Jen
2001	—	`conf`	An efficient 2-D DWT architecture via resource cycling. ISCAS (4) Tay-Jyi Lin, Chein-Wei Jen