Tatsuya Hirose

12 papers A* 1Journal 8Unranked 3
YearRankTypeTitle / Venue / Authors
2013 J jnl
Abstraction Multimodal Low-Dimensional Representation from High-Dimensional Posture Information and Visual Images.
J. Robotics Mechatronics
Tatsuya Hirose, Tadahiro Taniguchi
2013 A* conf
NTMobile: new end-to-end communication architecture in IPv4 and IPv6 networks.
MobiCom
Hidekazu Suzuki, Katsuhiro Naito, Kazuma Kamienoo, Tatsuya Hirose, Akira Watanabe
2012 J jnl
A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Yoichi Kawano, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa
2010 — conf
A 24 dB gain 51-68 GHz CMOS low noise amplifier using asymmetric-layout transistors.
ESSCIRC
Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa
2009 — conf
A 77GHz transceiver in 90nm CMOS.
ISSCC
Yoichi Kawano, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin
2009 J jnl
Advanced MMIC Receiver for 94-GHz Band Passive Millimeter-Wave Imager.
IEICE Trans. Electron.
Masaru Sato, Tatsuya Hirose, Koji Mizuno
2008 — conf
60 and 77GHz Power Amplifiers in Standard 90nm CMOS.
ISSCC
Toshihide Suzuki, Yoichi Kawano, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin
2007 J jnl
A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-µm InP HEMT Technology.
IEEE J. Solid State Circuits
Toshihide Suzuki, Yoichi Kawano, Yasuhiro Nakasha, Shinji Yamaura, Tsuyoshi Takahashi, Kozo Makiyama, Tatsuya Hirose
2005 J jnl
A 90-GHz InP-HEMT lossy match amplifier with a 20-dB gain using a broadband matching technique.
IEEE J. Solid State Circuits
Yusuke Inoue, Masaru Sato, Toshihiro Ohki, Kozo Makiyama, Tsuyoshi Takahashi, Hisao Shigematsu, Tatsuya Hirose
2004 J jnl
A 80-gbit/s D-type flip-flop circuit using InP HEMT technology.
IEEE J. Solid State Circuits
Toshihide Suzuki, Tsuyoshi Takahashi, Tatsuya Hirose, Masahiko Takikawa
2002 J jnl
A 43-Gb/s full-rate-clock 4: 1 multiplexer in InP-based HEMT technology.
IEEE J. Solid State Circuits
Yasuhiro Nakasha, Toshihide Suzuki, Hideki Kano, Kouji Tsukashima, Akio Ohya, Ken Sawada, Kozo Makiyama, Tsuyoshi Takahashi, Masahiro Nishi, Tatsuya Hirose, Masahiko Takikawa, Yuu Watanabe
2002 J jnl
A 54-GHz distributed amplifier with 6-V
IEEE J. Solid State Circuits
Hisao Shigematsu, Masaru Sato, Tatsuya Hirose, Yuu Watanabe