Tatsuo Shiozawa

11 papers B 1Journal 7Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
Analysis and Evaluation of Using Microsecond-Latency Memory for In-Memory Indices and Caches in SSD-Based Key-Value Stores.
CoRR
Yosuke Bando, Akinobu Mita, Kazuhiro Hiwada, Shintaro Sano, Tomoya Suzuki, Yu Nakanishi, Kazutaka Tomida, Hirotsugu Kajihara, Akiyuki Kaneko, Daisuke Taki, Yukimasa Miyamoto, Tomokazu Yoshida, Tatsuo Shiozawa
2025 J jnl
Analysis and Evaluation of Using Microsecond-Latency Memory for In-Memory Indices and Caches in SSD-Based Key-Value Stores.
Proc. ACM Manag. Data
Yosuke Bando, Akinobu Mita, Kazuhiro Hiwada, Shintaro Sano, Tomoya Suzuki, Yu Nakanishi, Kazutaka Tomida, Hirotsugu Kajihara, Akiyuki Kaneko, Daisuke Taki, Yukimasa Miyamoto, Tomokazu Yoshida, Tatsuo Shiozawa
2024 J jnl
Implementing and Evaluating E2LSH on Storage.
CoRR
Yu Nakanishi, Kazuhiro Hiwada, Yosuke Bando, Tomoya Suzuki, Hirotsugu Kajihara, Shintaro Sano, Tatsuro Endo, Tatsuo Shiozawa
2023 — conf
GPU Graph Processing on CXL-Based Microsecond-Latency External Memory.
SC Workshops
Shintaro Sano, Yosuke Bando, Kazuhiro Hiwada, Hirotsugu Kajihara, Tomoya Suzuki, Yu Nakanishi, Daisuke Taki, Akiyuki Kaneko, Tatsuo Shiozawa
2023 J jnl
GPU Graph Processing on CXL-Based Microsecond-Latency External Memory.
CoRR
Shintaro Sano, Yosuke Bando, Kazuhiro Hiwada, Hirotsugu Kajihara, Tomoya Suzuki, Yu Nakanishi, Daisuke Taki, Akiyuki Kaneko, Tatsuo Shiozawa
2023 B conf
Implementing and Evaluating E2LSH on Storage.
EDBT
Yu Nakanishi, Kazuhiro Hiwada, Yosuke Bando, Tomoya Suzuki, Hirotsugu Kajihara, Shintaro Sano, Tatsuro Endo, Tatsuo Shiozawa
2021 J jnl
Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses: a new access method and its graph applications.
Proc. VLDB Endow.
Tomoya Suzuki, Kazuhiro Hiwada, Hirotsugu Kajihara, Shintaro Sano, Shuou Nomura, Tatsuo Shiozawa
2013 J jnl
A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation.
IEICE Trans. Electron.
Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa
2012 — conf
An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation.
COOL Chips
Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa
2011 — conf
A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications.
COOL Chips
Daisuke Taki, Tatsuo Shiozawa, Kuniaki Ito, Youichiro Shiba, Kouji Horisaki, Hirotsugu Kajihara, Toshiyuki Yamagishi, Masahiro Sekiya, Akira Yamaga, Tetsuya Fujita, Hiroyuki Hara, Masanori Kuwahara, Toshio Fujisawa, Yasuo Unekawa
2003 J jnl
A single-chip 802.11a MAC/PHY with a 32-b RISC processor.
IEEE J. Solid State Circuits
Toshio Fujisawa, Jun Hasegawa, Koji Tsuchie, Tatsuo Shiozawa, Tetsuya Fujita, Toshitada Saito, Yasuo Unekawa