Tatsuo Ohtsuki

78 papers A* 1A 3B 1C 4Journal 39Unranked 30
YearRankTypeTitle / Venue / Authors
2012 J jnl
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis.
IEEE Trans. Very Large Scale Integr. Syst.
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2011 J jnl
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit.
Inf. Media Technol.
Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011 J jnl
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit.
IPSJ Trans. Syst. LSI Des. Methodol.
Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011 J jnl
A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures.
IPSJ Trans. Syst. LSI Des. Methodol.
Sho Tanaka, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011 J jnl
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems.
Inf. Media Technol.
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011 J jnl
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems.
IPSJ Trans. Syst. LSI Des. Methodol.
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011 J jnl
Scan Vulnerability in Elliptic Curve Cryptosystems.
IPSJ Trans. Syst. LSI Des. Methodol.
Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010 — conf
A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit.
APCCAS
Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2010 — conf
BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers.
APCCAS
Seungju Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2010 J jnl
Improved Launch for Higher TDF Coverage With Fewer Test Patterns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010 C conf
Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation.
ISCAS
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010 J jnl
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ryuta Nara, Kei Satoh, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2010 — conf
Scan-based attack against elliptic curve cryptosystems.
ASP-DAC
Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010 C conf
State-dependent changeable scan architecture against scan-based side channel attacks.
ISCAS
Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010 — conf
VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding.
APCCAS
Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009 J jnl
A Scan-Based Attack Based on Discriminators for AES Cryptosystems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009 J jnl
A Two-Level Cache Design Space Exploration System for Embedded Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009 J jnl
An L1 Cache Design Space Exploration System for Embedded Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009 A conf
Design-for-secure-test for crypto cores.
ITC
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009 — conf
Exact and fast L1 cache simulation for embedded systems.
ASP-DAC
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009 J jnl
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009 J jnl
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009 J jnl
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 J jnl
A Secure Test Technique for Pipelined Advanced Encryption Standard.
IEICE Trans. Inf. Syst.
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 J jnl
A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 — conf
Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding.
APCCAS
Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 — conf
FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm.
APCCAS
Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Makoto Satoh
2008 J jnl
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures.
Inf. Media Technol.
Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 J jnl
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures.
IPSJ Trans. Syst. LSI Des. Methodol.
Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 — conf
GECOM: Test data compression combined with all unknown response masking.
ASP-DAC
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 — conf
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2
ASP-DAC
Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 — conf
Unknown response masking with minimized observable response loss and mask data.
APCCAS
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2007 C conf
Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard.
ISCAS
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2006 J jnl
A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier.
IEICE Trans. Electron.
Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2006 — conf
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs.
ASP-DAC
Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2006 — conf
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction.
ASP-DAC
Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2006 J jnl
Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2005 J jnl
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition.
IEICE Trans. Inf. Syst.
Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2005 — conf
A processor core synthesis system in IP-based SoC design.
ASP-DAC
Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2005 — conf
Low Power Test Compression Technique for Designs with Multiple Scan Chain.
Asian Test Symposium
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura
2005 J jnl
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2005 — conf
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations.
ISCAS (4)
Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2004 — conf
A cosynthesis algorithm for application specific processors with heterogeneous datapaths.
ASP-DAC
Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2004 — conf
A thread partitioning algorithm in low power high-level synthesis.
ASP-DAC
Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2004 — conf
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test.
Asian Test Symposium
Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2004 — conf
Instruction set and functional unit synthesis for SIMD processor cores.
ASP-DAC
Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2003 J jnl
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2003 J jnl
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Nozomu Togawa, Takao Totsuka, Tatsuhiko Wakui, Masao Yanagisawa, Tatsuo Ohtsuki
2003 J jnl
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2003 J jnl
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Nozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki
2003 — conf
A hardware/software partitioning algorithm for SIMD processor cores.
ASP-DAC
Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki
2002 J jnl
A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2002 J jnl
An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2002 — conf
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.
APCCAS (1)
Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2002 J jnl
High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2002 — conf
VLSI Architecture for a Flexible Motion Estimation with Parameters.
ASP-DAC/VLSI Design
Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2001 — conf
Area/delay estimation for digital signal processor cores.
ASP-DAC
Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2000 — conf
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper).
ASP-DAC
Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki
1999 — conf
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing.
ASP-DAC
Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki
1999 J jnl
A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization.
J. Circuits Syst. Comput.
Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki
1999 J jnl
Fast Motion Estimation Scheme for Video Coding Using Feature Vector Matching and Motion Vector's Correlations.
J. Circuits Syst. Comput.
Tingrong Zhao, Masao Yanagisawa, Tatsuo Ohtsuki
1998 — conf
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs.
ASP-DAC
Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki
1998 — conf
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays.
ASP-DAC
Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki
1998 J jnl
Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
1997 J jnl
A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems.
J. Circuits Syst. Comput.
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
1997 — conf
A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs.
ASP-DAC
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
1995 — conf
Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization.
ASP-DAC
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
1994 C conf
A Simultaneous Placement and Global Routing Algorithm for FPGAs.
ISCAS
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
1994 A conf
A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays.
ICCAD
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
1992 A conf
An optimal chip compaction method based on shortest path algorithm with automatic jog insertion.
ICCAD
Toru Awashima, Wataru Yamamoto, Masao Sato, Tatsuo Ohtsuki
1990 A* conf
A Hardware Implementation of Gridless Routing Based on Content Addressable Memory.
DAC
Masao Sato, Kazuto Kubota, Tatsuo Ohtsuki
1990 J jnl
Recent advances in VLSI layout.
Proc. IEEE
Ernest S. Kuh, Tatsuo Ohtsuki
1987 J jnl
Applications of computational geometry to VLSI layout pattern design.
Integr.
Masao Sato, Tatsuo Ohtsuki
1986 J jnl
A Hardware Maze Router with Application to Interactive Rip-Up and Reroute.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki
1981 J jnl
On Minimal Augmentation of a Graph to Obtain an Interval Graph.
J. Comput. Syst. Sci.
Tatsuo Ohtsuki, Hajimu Mori, Toshinobu Kashiwabara, Toshio Fujisawa
1980 — conf
The two disjoint path problem and wire routing design.
Graph Theory and Algorithms
Tatsuo Ohtsuki
1979 B conf
One-dimensional logic gate assignment and interval graphs.
COMPSAC
Tatsuo Ohtsuki, Hajimu Mori, Ernest S. Kuh, Toshinobu Kashiwabara, Toshio Fujisawa
1976 J jnl
A Fast Algorithm for Finding an Optimal Ordering for Vertex Elimination on a Graph.
SIAM J. Comput.
Tatsuo Ohtsuki