Tatsuo Higuchi

142 papers A* 1A 2B 4C 7Misc 8Journal 65Unranked 55

Year	Rank	Type	Title / Venue / Authors
2010	J	`jnl`	Score-Level Fusion of Phase-Based and Feature-Based Fingerprint Matching Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koichi Ito, Ayumi Morita, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi, Tatsuo Higuchi
2009	J	`jnl`	Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. J. Multiple Valued Log. Soft Comput. Naofumi Homma, Yuki Watanabe, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2009	J	`jnl`	Toward Biomolecular Computers Using Reaction-Diffusion Dynamics. Int. J. Nanotechnol. Mol. Comput. Masahiko Hiratsuka, Koichi Ito, Takafumi Aoki, Tatsuo Higuchi
2008	J	`jnl`	A Palmprint Recognition Algorithm Using Phase-Only Correlation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koichi Ito, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi, Tatsuo Higuchi
2008	J	`jnl`	A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams. IEEE Trans. Computers Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2008	J	`jnl`	Arithmetic Circuit Verification Based on Symbolic Computer Algebra. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2008	C	`conf`	Arithmetic module generator with algorithm optimization capability. ISCAS Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2008	—	`conf`	High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. ISMVL Yuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2008	J	`jnl`	Shortest Path Search Using a Reaction-Diffusion Processor. Int. J. Unconv. Comput. Masahiko Hiratsuka, Koichi Ito, Takafumi Aoki, Tatsuo Higuchi
2007	—	`conf`	Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. ISMVL Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2007	C	`conf`	Application of symbolic computer algebra to arithmetic circuit verification. ICCD Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2007	J	`jnl`	Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams. J. Multiple Valued Log. Soft Comput. Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2007	J	`jnl`	Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors. J. Multiple Valued Log. Soft Comput. Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
2007	J	`jnl`	Synthesis of current mirrors based on evolutionary graph generation with transmigration capability. IEICE Electron. Express Masanori Natsui, Yoshiaki Tadokoro, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2006	—	`conf`	A Fingerprint Recognition Algorithm Combining Phase-Based Image Matching and Feature-Based Matching. ICB Koichi Ito, Ayumi Morita, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi, Tatsuo Higuchi
2006	—	`conf`	A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. ISMVL Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi
2006	B	`conf`	A Palmprint Recognition Algorithm using Phase-Based Image Matching. ICIP Koichi Ito, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi, Tatsuo Higuchi
2006	J	`jnl`	A Shortest Path Search Algorithm Using an Excitable Digital Reaction-Diffusion System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koichi Ito, Masahiko Hiratsuka, Takafumi Aoki, Tatsuo Higuchi
2006	—	`conf`	Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic. ISMVL Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2006	—	`conf`	Fast and Robust Fingerprint Identification Algorithm and Its Application to Residential Access Controller. ICB Hiroshi Nakajima, Koji Kobayashi, Makoto Morikawa, Atsushi Katsumata, Koichi Ito, Takafumi Aoki, Tatsuo Higuchi
2006	J	`jnl`	Formal Design of Arithmetic Circuits Based on Arithmetic Description Language. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Naofumi Homma, Yuki Watanabe, Takafumi Aoki, Tatsuo Higuchi
2006	J	`jnl`	Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic. IEICE Trans. Electron. Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2005	—	`conf`	A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. ISMVL Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi
2005	J	`jnl`	A compact cluster computer with embedded CPUs and its application to rapid prototyping of fingerprint verification system. IEICE Electron. Express Yoshifumi Sasaki, Koichi Ito, Takafumi Aoki, Tatsuo Higuchi
2005	—	`conf`	A fingerprint recognition algorithm using phase-based image matching for low-quality fingerprints. ICIP (2) Koichi Ito, Ayumi Morita, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Nakajima, Koji Kobayashi
2005	J	`jnl`	Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis. J. Multiple Valued Log. Soft Comput. Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2005	J	`jnl`	Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects. J. Multiple Valued Log. Soft Comput. Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2004	—	`conf`	A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. ISMVL Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
2004	—	`conf`	A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. ISMVL Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2004	—	`conf`	A systematic approach for analyzing fast addition algorithms using counter tree diagrams. ISCAS (5) Naofumi Homma, Jun Sakiyama, Taihei Wakamatsu, Takafumi Aoki, Tatsuo Higuchi
2004	—	`conf`	Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH. ISMVL Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2004	—	`conf`	Multiplier Block Synthesis Using Evolutionary Graph Generation. Evolvable Hardware Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2004	A	`conf`	Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation. PPSN Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2003	—	`conf`	A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic. ISMVL Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2003	—	`conf`	A framework of evolutionary graph generation system and its application to circuit synthesis. ISCAS (5) Naofumi Homma, Takafumi Aoki, Makoto Motegi, Tatsuo Higuchi
2003	—	`conf`	Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms. ISMVL Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi
2003	J	`jnl`	Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jun Sakiyama, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2003	J	`jnl`	Counter Tree Diagrams: A Unified Representation of Fast Addition Algorithms. J. Multiple Valued Log. Soft Comput. Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi
2003	J	`jnl`	Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2003	—	`conf`	Design of a digital reaction-diffusion system for restoring blurred fingerprint images. ISCAS (4) Koichi Ito, Takafumi Aoki, Tatsuo Higuchi
2003	J	`jnl`	Evolutionary Synthesis of Arithmetic Circuit Structures. Artif. Intell. Rev. Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi
2003	J	`jnl`	Fingerprint Restoration Using Digital Reaction-Diffusion System and Its Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koichi Ito, Takafumi Aoki, Tatsuo Higuchi
2003	J	`jnl`	High-Accuracy Subpixel Image Registration Based on Phase-Only Correlation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kenji Takita, Takafumi Aoki, Yoshifumi Sasaki, Tatsuo Higuchi, Koji Kobayashi
2003	B	`conf`	VLSI circuit design using an object-oriented framework of evolutionary graph generation system. IEEE Congress on Evolutionary Computation Naofumi Homma, Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
2002	—	`conf`	An LVQ-based technique for human motion segmentation. APCCAS (2) Mochamad Hariadi, Akio Harada, Takafumi Aoki, Tatsuo Higuchi
2002	A	`conf`	Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis. PPSN Makoto Motegi, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2002	J	`jnl`	Graph-based evolutionary design of arithmetic circuits. IEEE Trans. Evol. Comput. Dingjun Chen, Takafumi Aoki, Naofumi Homma, Toshiki Terasaki, Tatsuo Higuchi
2002	B	`conf`	Graph-based individual representation for evolutionary synthesis of arithmetic circuits. IEEE Congress on Evolutionary Computation Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2002	—	`conf`	Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI. ISMVL Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi
2002	J	`jnl`	Parallel Evolutionary Design of Constant-Coefficient Multipliers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Dingjun Chen, Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi
2002	J	`jnl`	Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
2002	—	`conf`	Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis. ISMVL Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
2002	C	`conf`	Pixel-wise human motion segmentation using learning vector quantization. ICARCV Mochamad Hariadi, Akio Harada, Takafumi Aoki, Tatsuo Higuchi
2001	—	`conf`	A Model of Reaction-Diffusion Cellular Automata for Massively Parallel Molecular Computing. ISMVL Masahiko Hiratsuka, Takafumi Aoki, Tatsuo Higuchi
2001	—	`conf`	Distributed evolutionary design of constant-coefficient multipliers. ICECS Dingjun Chen, Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi
2001	—	`conf`	Evolutionary graph generation system with transmigration capability for arithmetic circuit design. ISCAS (5) Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2001	—	`conf`	Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation. ISMVL Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
2000	—	`conf`	An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access. ISMVL Yasushi Yuminaka, Osamu Katoh, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi
2000	—	`conf`	High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables. ISMVL Takafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi
1999	—	`conf`	Redundant Complex Arithmetic and Its Application to Complex Multiplier Design. ISMVL Takafumi Aoki, Ken-ichi Hoshi, Tatsuo Higuchi
1998	—	`conf`	Set-Valued Logic Circuits for Next Generation VLSI Architectures. ISMVL Takafumi Aoki, Tatsuo Higuchi
1998	—	`conf`	Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences. ISMVL Yasushi Yuminaka, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi
1997	J	`jnl`	Communication network protocol for real-time distributed control and its LSI implementation. IEEE Trans. Ind. Electron. Koji Kobayashi, Michitaka Kameyama, Tatsuo Higuchi
1997	—	`conf`	Enzyme Transistor Circuits for Biomolecular Computing. ISMVL Masahiko Hiratsuka, Takafumi Aoki, Tatsuo Higuchi
1997	C	`conf`	Real/Complex Reconfigurable Arithmetic Using Redundant Complex Number Systems. IEEE Symposium on Computer Arithmetic Takafumi Aoki, Hiroaki Amada, Tatsuo Higuchi
1996	J	`jnl`	Author's Reply. IEEE Trans. Computers Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi
1996	J	`jnl`	Efficient learning of NN-MLP based on individual evolutionary algorithm. Neurocomputing Qiangfu Zhao, Tatsuo Higuchi
1996	J	`jnl`	Evolutionary learning of nearest-neighbor MLP. IEEE Trans. Neural Networks Qiangfu Zhao, Tatsuo Higuchi
1996	Misc	`conf`	GA-based design of multiplierless 2-D state-space digital filters with very small roundoff noise. ICASSP Young-Ho Lee, Masayuki Kawamata, Tatsuo Higuchi
1996	J	`jnl`	Minimization of nearest neighbor classifiers based on individual evolutionary algorithm. Pattern Recognit. Lett. Qiangfu Zhao, Tatsuo Higuchi
1996	—	`conf`	Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves. ISMVL Yasushi Yuminaka, Yoshisato Sasaki, Takafumi Aoki, Tatsuo Higuchi
1995	—	`conf`	An Evolutionary Algorithm for Solving Multi-Individual-Multi-Task Problems. BIES Qiangfu Zhao, Tatsuo Higuchi
1995	B	`conf`	Design of 2-D state-space digital filters with powers-of-two coefficients based on a genetic algorithm. ICIP Young-Ho Lee, Masayuki Kawamata, Tatsuo Higuchi
1995	Misc	`conf`	Individual Evolutionary Algorithm and its Application to Learning of Nearest Neighbor Based MLP. IWANN Qiangfu Zhao, Tatsuo Higuchi
1995	—	`conf`	Multiwave Interconnection Networks for MCM-based Parallel Processing. Euro-Par Shinichi Shionoya, Takafumi Aoki, Tatsuo Higuchi
1995	—	`conf`	Redundant Complex Number Systems. ISMVL Yuji Ohi, Takafumi Aoki, Tatsuo Higuchi
1995	—	`conf`	Wire-Free Computing Circuits Using Optical Wave-Casting. ISMVL S. Sakurai, Takafumi Aoki, Tatsuo Higuchi
1994	J	`jnl`	Coordinate Transformation VLSI Processor for Redundant Manipulator Control. J. Robotics Mechatronics Yoshichika Fujioka, Michitaka Kameyama, Tatsuo Higuchi
1994	—	`conf`	Design of Multiplex Interconnection Networks for Massively Parallel Computing Systems. ISMVL Takashi Takimoto, Takafumi Aoki, Tatsuo Higuchi
1994	—	`conf`	Design of Multiwave Computing Circuits Based on a Modle of Integrated Opto-Electronic Devices. ISMVL Yukio Watanabe, Takafumi Aoki, Tatsuo Higuchi
1994	—	`conf`	Design of Wave-Parallel Computing Circuits for Densely Connected Architectures. ISMVL Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
1994	J	`jnl`	Design of an Intelligent Fault-Tolerant System for Real-World Applications. J. Robotics Mechatronics Shigeki Abe, Michitaka Kameyama, Tatsuo Higuchi
1994	J	`jnl`	High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. IEEE Trans. Computers Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi
1994	—	`conf`	Multi-resolution Tree Search for Iterated Transformation Theory-Based Coding. ICIP (3) Masayuki Kawamata, Masaki Nagahisa, Tatsuo Higuchi
1994	—	`conf`	Optimal Design Method of 2-D IIR Digital Filters Based on a Simple Genetic Algorithm. ICIP (1) Masayuki Kawamata, Jun Imakubo, Tatsuo Higuchi
1993	—	`conf`	A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions. ISMVL Satoshi Aragaki, Takahiro Hanyu, Tatsuo Higuchi
1993	J	`jnl`	Design of 2-d Digital filters Based on the Optimal Decomposition of Magnitude Specifications. J. Circuits Syst. Comput. Tian-Bo Deng, Masayuki Kawamata, Tatsuo Higuchi
1993	C	`conf`	Design of Fine Grain VLSI Array Processor for Real-time 2-D Digital Filtering. ISCAS Yasushi Iwata, Masayuki Kawamata, Tatsuo Higuchi
1993	—	`conf`	Design of Set-Valued Logic Networks for Wave-Parallel Computing. ISMVL Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
1993	—	`conf`	Impact of Interconnection-Free Biomolecular Computing. ISMVL Takafumi Aoki, Tatsuo Higuchi
1993	J	`jnl`	Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations. Syst. Comput. Jpn. Shoui Kaqahito, Makoto Ishida, Tetsuro Nakamura, Kentaro Mizuno, Michitaka Kameyama, Tatsuo Higuchi
1993	C	`conf`	Realization of lattice-form separable-denominator 2D adaptive filters. ISCAS Masayuki Kawamata, Eiichiro Kawakami, Tatsuo Higuchi
1992	—	`conf`	Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits. ISMVL Saneaki Tamaki, Michitaka Kameyama, Tatsuo Higuchi
1992	—	`conf`	Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. ISMVL Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi
1992	—	`conf`	Design of a Multiple-Valued VLSI Processor for Digital Control. ISMVL Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi
1992	J	`jnl`	Design of an ultrahigher-valued biocomputing system based on set-valued logic networks. Syst. Comput. Jpn. Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi
1992	J	`jnl`	Highly parallel collision detection processor for intelligent robots. IEEE J. Solid State Circuits Michitaka Kameyama, Tadao Amada, Tatsuo Higuchi
1992	J	`jnl`	Interconnection-Free Biomolecular Computing. Computer Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi
1992	—	`conf`	Residue Arithmetic Based Multiple-Valued VLSI Image Processor. ISMVL Makoto Honda, Michitaka Kameyama, Tatsuo Higuchi
1992	—	`conf`	Set-Valued Logic Networks Based on Optical Wavelength Multiplexing. ISMVL Shuichi Maeda, Takafumi Aoki, Tatsuo Higuchi
1991	—	`conf`	A Floating-Gate-MOS-Based Multiple-Valued Associative Memory. ISMVL Takahiro Hanyu, Tatsuo Higuchi
1991	—	`conf`	A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems. ISMVL Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi
1991	—	`conf`	Design of Interconnection-Free Biomolecular Computing System. ISMVL Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi
1991	—	`conf`	Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing. ISMVL Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
1991	J	`jnl`	Design of a robust fault-tolerant multiplier. Syst. Comput. Jpn. Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi
1991	C	`conf`	High-Performance VLSI Processor for Robot Inverse Dynamics Computation. ICCD Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi
1991	J	`jnl`	Performance evaluation of a multivalued rsa encryption vlsi. Syst. Comput. Jpn. Shugang Wei, Michitaka Kameyama, Tatsuo Higuchi
1990	—	`conf`	Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices. ISMVL Takahiro Hanyu, Tatsuo Higuchi
1990	J	`jnl`	Design of a Highly Parallel Ultrahigher-Valued Logic Network Based on a Bio-Device Model. Syst. Comput. Jpn. Michitaka Kameyama, Takafumi Aoki, Tatsuo Higuchi
1990	J	`jnl`	Design of a Matrix Multiply-Addition VLSI Processor for Robot control. J. Robotics Mechatronics Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi
1990	J	`jnl`	Design of a Parallel Collision Detection Check VLSI Processor for Robot Manipulator. J. Robotics Mechatronics Tadao Amada, Michitaka Kameyama, Tatsuo Higuchi
1990	J	`jnl`	Design of a fault-tolerant arithmetic circuit based on distributed coding and its evaluation. Syst. Comput. Jpn. Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi
1990	J	`jnl`	Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits. Syst. Comput. Jpn. Michitaka Kameyama, Shugang Wei, Tatsuo Higuchi
1990	J	`jnl`	High-Performance LSI for Kinematics Computation. J. Robotics Mechatronics Tatsuo Higuchi
1990	—	`conf`	Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. ISMVL Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi
1990	J	`jnl`	Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems. IEEE J. Solid State Circuits Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi
1990	J	`jnl`	Robot Electronics System. J. Robotics Mechatronics Tatsuo Higuchi, Michitaka Kameyama
1989	J	`jnl`	Bi-directional current-mode basic circuits for the multilevel signed-digit arithmetic and their evaluation. Syst. Comput. Jpn. Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi
1989	J	`jnl`	Design of a Multiple-Valued Associative Memory. Syst. Comput. Jpn. Takahiro Hanyu, Tatsuo Higuchi
1989	J	`jnl`	High-density quaternary logic array chip for knowledge information processing systems. IEEE J. Solid State Circuits Takahiro Hanyu, Tatsuo Higuchi
1989	J	`jnl`	Highly parallel residue arithmetic chip based on multiple-valued bidirectional current-mode logic. IEEE J. Solid State Circuits Michitaka Kameyama, Tsutomu Sekibe, Tatsuo Higuchi
1989	A*	`conf`	Implementation of a high performance LSI for inverse kinematics computation. ICRA Michitaka Kameyama, Takao Matsumoto, Hideki Egami, Tatsuo Higuchi
1989	J	`jnl`	VLSI Computer for Robotics. J. Robotics Mechatronics Michitaka Kameyama, Tatsuo Higuchi
1988	J	`jnl`	A 32*32-bit multiplier using multiple-valued MOS current-mode circuits. IEEE J. Solid State Circuits Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi, Haruyasu Yamada
1988	J	`jnl`	A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits. Computer Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi
1988	J	`jnl`	Design of a Fault-Tolerant System Based on Knowledge-Engineering Approach and Its Application to a Digital Control System. Syst. Comput. Jpn. Michitaka Kameyama, Li Zheng, Tatsuo Higuchi
1988	J	`jnl`	Design of a time-optimal digital control system for a dc-servomotor with amplitude limitation. Syst. Comput. Jpn. Xi Yue Huang, Michitaka Kameyama, Tatsuo Higuchi
1987	J	`jnl`	Design and implementation of an nmos image processor based on quaternary logic. Syst. Comput. Jpn. Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi
1987	J	`jnl`	Design of VLSI-oriented radix-4 signed-digit arithmetic circuits using multiple-valued logic. Syst. Comput. Jpn. Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi
1987	J	`jnl`	Design of micropower CMOS quaternary memory circuits. Syst. Comput. Jpn. Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi
1986	Misc	`conf`	A unified design method of state-space digital filters using system balancing concept. ICASSP Qiangfu Zhao, Masayuki Kawamata, Tatsuo Higuchi
1986	Misc	`conf`	A unified study on the roundoff noise in 2-D state space digital filters. ICASSP Tao Lin, Masayuki Kawamata, Tatsuo Higuchi
1986	J	`jnl`	Design of low-power quaternary CMOS logic circuits. Syst. Comput. Jpn. Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi
1986	J	`jnl`	Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits. Syst. Comput. Jpn. Nobuhiro Tomabechi, Michitaka Kameyama, Tatsuo Higuchi
1986	Misc	`conf`	Synthesis of minimum sensitivity structures in linear systems using controllability and observability measures. ICASSP Masami Iwatsuki, Masayuki Kawamata, Tatsuo Higuchi
1985	J	`jnl`	A unified approach to the optimal synthesis of fixed-point state-space digital filters. IEEE Trans. Acoust. Speech Signal Process. Masayuki Kawamata, Tatsuo Higuchi
1981	Misc	`conf`	Another discrete Fourier transform computation with small multiplications via the Walsh transform. ICASSP Yoshiaki Tadokoro, Tatsuo Higuchi
1980	Misc	`conf`	A sufficient condition for absence of overflow oscillations in arbitrary digital filters based on the element equations. ICASSP Masayuki Kawamata, Tatsuo Higuchi
1979	Misc	`conf`	A state-space approach for elimination of limit cycles in digital filters with arbitrary structures. ICASSP Tatsuo Higuchi, Hiroski Takeo
1978	—	`conf`	Special-purpose ternary computer for digital filtering. MVL Tatsuo Higuchi, Hisamitsu Hoshi
1977	J	`jnl`	Static-Hazard-Free IEEE Trans. Computers Tatsuo Higuchi, Michitaka Kameyama
1977	J	`jnl`	Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module. IEEE Trans. Computers Michitaka Kameyama, Tatsuo Higuchi