Tatsuji Matsuura

43 papers Journal 19Unranked 24

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Eiki Kayama, Kenta Mori, Taichi Maebou, Yuanchi Chen, Hao San, Tatsuji Matsuura, Masao Hotta
2021	—	`conf`	A 0.7V 14bit Hybrid ADC in 65nm SOTB CMOS. ISPACS Taichi Maebou, Yuanchi Chen, Eiki Kayama, Kenta Mori, Hao San, Tatsuji Matsuura, Masao Hotta
2021	—	`conf`	A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology. ISPACS Eiki Kayama, Kenta Mori, Taichi Maebou, Yuanchi Chen, Hao San, Tatsuji Matsuura, Masao Hotta
2021	—	`conf`	A Low-voltage Non-binary Cyclic ADC using Fully Differential Ring Amplifier. ISPACS Kenta Mori, Eiki Kayama, Taichi Maebou, Yuanchi Chen, Hao San, Tatsuji Matsuura, Masao Hotta
2021	J	`jnl`	Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Satoshi Sekine, Tatsuji Matsuura, Ryo Kishida, Akira Hyogo
2019	—	`conf`	A 0.8V 14bit 62.5kSPS non-binary cyclic ADC using SOTB CMOS technology. ISPACS Shuichiro Yamada, Toshiki Ohtsu, Minami Sasaki, Hao San, Tatsuji Matsuura, Masao Hotta
2019	—	`conf`	Duty Ratio and Capacitance Analysis of AC/DC Converter without Current Control Circuit. ISPACS Yuki Tanaka, Tatsuji Matsuura, Ryo Kishida, Akira Hyogo
2019	—	`conf`	Examination of Incremental ADC with SAR ADC to Reduce Conversion Time with High Accuracy. ISPACS Yuichiro Unno, Tatsuji Matsuura, Ryo Kishida, Akira Hyogo
2019	—	`conf`	Investigation of Hybrid ADC Combined with First-order Feedforward Incremental and SAR ADCs. ISPACS Yuichiro Kobayashi, Tatsuji Matsuura, Ryo Kishida, Akira Hyogo
2018	—	`conf`	A Novel C-2αC Ladder Based Non-binary DAC for SAR-ADC Using Unit Capacitors. ISPACS Satoshi Sekine, Tatsuji Matsuura, Ryo Kishida, Akira Hyogo
2017	—	`conf`	A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique. ISPACS Koken Chin, Yuta Mishima, Yuki Watanabe, Hiroyuki Tsuchiya, Hao San, Tatsuji Matsuura, Masao Hotta
2017	J	`jnl`	A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hao San, Rompei Sugawara, Masao Hotta, Tatsuji Matsuura, Kazuyuki Aihara
2017	—	`conf`	A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components. ASP-DAC Yuki Watanabe, Hayato Narita, Hiroyuki Tsuchiya, Tatsuji Matsuura, Hao San, Masao Hotta
2017	—	`conf`	Experimental results of reconfigurable non-binary cyclic ADC. ISPACS Yuki Watanabe, Koken Chin, Hiroyuki Tsuchiya, Hao San, Tatsuji Matsuura, Masao Hotta
2017	—	`conf`	Integrated CMOS ADC - Tutorial review on recent hybrid SAR-ADCs. MIXDES Tatsuji Matsuura
2017	—	`conf`	Non-binary cyclic ADC with correlated level shifting technique. ASP-DAC Hiroyuki Tsuchiya, Asato Uchiyama, Yuta Misima, Yuki Watanabe, Tatsuji Matsuura, Hao San, Masao Hotta
2017	—	`conf`	Non-binary cyclic and binary SAR hybrid ADC. MIXDES Kota Inoue, Tatsuji Matsuura, Akira Hyogo, Hao San
2017	—	`conf`	The design of a 14-bit 400kSPS non-binary pipeline cyclic ADC. ISPACS Hiroyuki Tsuchiya, Yuki Watanabe, Koken Chin, Hao San, Tatsuji Matsuura, Masao Hotta
2016	J	`jnl`	A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Junya Matsuno, Masanori Furuta, Tetsuro Itakura, Tatsuji Matsuura, Akira Hyogo
2015	—	`conf`	A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion. ISPACS Yuta Mishima, Toshiki Yamada, Asato Uchiyama, Tatsuji Matsuura, Hao San, Masao Hotta
2014	J	`jnl`	A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver. IEEE J. Solid State Circuits Hideo Nakane, Ryuichi Ujiie, Takashi Oshima, Takaya Yamamoto, Keisuke Kimura, Yuichi Okuda, Kosuke Tsuiji, Tatsuji Matsuura
2014	—	`conf`	An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components. CICC Hao San, Rompei Sugawara, Masao Hotta, Tatsuji Matsuura, Kazuyuki Aihara
2013	J	`jnl`	Multi-bit Sigma-Delta TDC Architecture with Improved Linearity. J. Electron. Test. Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Daiki Hirabayashi, Yuta Arakawa, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuji Yano, Tatsuhiro Gake, Takahiro J. Yamaguchi, Nobukazu Takai
2012	—	`conf`	Multi-bit sigma-delta TDC architecture with self-calibration. APCCAS Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuta Arakawa, Daiki Hirabayashi, Yuji Yano, Tatsuhiro Gake, Nobukazu Takai, Takahiro J. Yamaguchi
2011	J	`jnl`	Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme. IEICE Trans. Electron. Takuya Yagi, Kunihiko Usui, Tatsuji Matsuura, Satoshi Uemori, Satoshi Ito, Yohei Tan, Haruo Kobayashi
2010	—	`conf`	Background calibration algorithm for pipelined ADC with open-loop residue amplifier using split ADC structure. APCCAS Takuya Yagi, Kunihiko Usui, Tatsuji Matsuura, Satoshi Uemori, Yohei Tan, Satoshi Ito, Haruo Kobayashi
2010	—	`conf`	Non-binary SAR ADC with digital error correction for low power applications. APCCAS Tomohiko Ogawa, Tatsuji Matsuura, Haruo Kobayashi, Nobukazu Takai, Masao Hotta, Hao San, Akira Abe, Katsuyoshi Yagi, Toshihiko Mori
2010	J	`jnl`	SAR ADC Algorithm with Redundancy and Digital Error Correction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tomohiko Ogawa, Haruo Kobayashi, Yosuke Takahashi, Nobukazu Takai, Masao Hotta, Hao San, Tatsuji Matsuura, Akira Abe, Katsuyoshi Yagi, Toshihiko Mori
2010	—	`conf`	SAR ADC that is configurable to optimize yield. APCCAS Tomohiko Ogawa, Haruo Kobayashi, Yohei Tan, Satoshi Ito, Satoshi Uemori, Nobukazu Takai, Kiichi Niitsu, Takahiro J. Yamaguchi, Tatsuji Matsuura, Nobuyoshi Ishikawa
2009	J	`jnl`	1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver. IEICE Trans. Electron. Tatsuo Nakagawa, Tatsuji Matsuura, Eiki Imaizumi, Junya Kudoh, Goichi Ono, Masayuki Miyazaki
2008	J	`jnl`	A 63 mA 112/94 dB DR IF Bandpass ΔΣ Modulator With Direct Feed-Forward Compensation and Double Sampling. IEEE J. Solid State Circuits Takaya Yamamoto, Masumi Kasahara, Tatsuji Matsuura
2007	—	`conf`	1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiver. ESSCIRC Tatsuo Nakagawa, Tatsuji Matsuura, Eiki Imaizumi, Junya Kudoh, Goichi Ono, Masayuki Miyazaki, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura
2007	—	`conf`	A 63-mA 112/94-dB DR IF bandpass ΔΣ modulator with direct feed-forward and double sampling. CICC Takaya Yamamoto, Masumi Kasahara, Tatsuji Matsuura
2007	J	`jnl`	A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. IEICE Trans. Electron. Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada
2007	—	`conf`	ΔΣ ADCs and Converter Techniques. ISSCC Zhongyuan Chang, Tatsuji Matsuura
2006	J	`jnl`	A Novel False Lock Detection Technique for a Wide Frequency Range Delay-Locked Loop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasutoshi Aibara, Eiki Imaizumi, Hiroaki Takagishi, Tatsuji Matsuura
2006	J	`jnl`	Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hao San, Akira Hayakawa, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Kazuyuki Kobayashi, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada
2006	J	`jnl`	Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use. IEICE Trans. Electron. Masao Hotta, Tatsuji Matsuura
1998	J	`jnl`	A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter. IEEE J. Solid State Circuits Tatsuji Matsuura, Takashi Nara, Tatsuya Komatsu, Eiki Imaizumi, Toshihiro Matsutsuru, Ryutaro Horita, Haruto Katsu, Shintaro Suzumura, Kazuo Sato
1997	J	`jnl`	Error suppressing encode logic of FCDL in a 6-b flash A/D converter. IEEE J. Solid State Circuits Koichi Ono, Tatsuji Matsuura, Eiki Imaizumi, Hisashi Okazawa, Ryuushi Shimokawa
1996	J	`jnl`	Correction to "Voltage-Comparator-Based Measurement of Equivalentiy Samlpled Substrate Noise Wavefor. IEEE J. Solid State Circuits Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta
1996	J	`jnl`	Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits. IEEE J. Solid State Circuits Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta
1995	J	`jnl`	Measurement of digital noise in mixed-signal integrated circuits. IEEE J. Solid State Circuits Keiko Makie-Fukuda, Takafumi Kikuchi, Tatsuji Matsuura, Masao Hotta