Tarun Kumar Gupta

21 papers C 1Journal 19Unranked 1
YearRankTypeTitle / Venue / Authors
2024 J jnl
DeLTran15: A Deep Lightweight Transformer-Based Framework for Multiclass Classification of Disaster Posts on X.
IEEE Access
Saima Saleem, Nabeela Hasan, Anuradha Khattar, Priti Rai Jain, Tarun Kumar Gupta, Monica Mehrotra
2023 J jnl
BatTS: a hybrid method for optimizing deep feedforward neural network.
PeerJ Comput. Sci.
Sichen Pan, Tarun Kumar Gupta, Khalid Raza
2023 J jnl
Impact of temperature variation on noise parameters and HCI degradation of Recessed Source/Drain Junctionless Gate All Around MOSFETs.
Microelectron. J.
Alok Kumar, Tarun Kumar Gupta, Bhavana P. Shrivastava, Abhinav Gupta
2023 J jnl
Noise and linearity analysis of recessed-source/drain junctionless Gate All Around (Re-S/D-JL-GAA) MOSFETs for communication systems.
Microelectron. J.
Alok Kumar, Tarun Kumar Gupta, Bhavana P. Shrivastava, Abhinav Gupta
2022 J jnl
Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor.
J. Circuits Syst. Comput.
Yogesh Shrivastava, Tarun Kumar Gupta
2021 C conf
Optimization of Artificial Neural Network: A Bat Algorithm-Based Approach.
ISDA
Tarun Kumar Gupta, Khalid Raza
2020 J jnl
A 1-bit full adder using CNFET based dual chirality high speed domino logic.
Int. J. Circuit Theory Appl.
Sandeep Garg, Tarun Kumar Gupta, Amit Kumar Pandey
2020 J jnl
A novel high-density dual threshold GNRFET SRAM design with improved stability.
Microprocess. Microsystems
Pramod Kumar Patel, M. M. Malik, Tarun Kumar Gupta
2020 J jnl
Optimizing Deep Feedforward Neural Network Architecture: A Tabu Search Based Approach.
Neural Process. Lett.
Tarun Kumar Gupta, Khalid Raza
2019 J jnl
A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology.
J. Circuits Syst. Comput.
Sandeep Garg, Tarun Kumar Gupta
2019 J jnl
FDSTDL: Low-power technique for FinFET domino circuits.
Int. J. Circuit Theory Appl.
Sandeep Garg, Tarun Kumar Gupta
2019 J jnl
Low leakage domino logic circuit for wide fan-in gates using CNTFET.
IET Circuits Devices Syst.
Sandeep Garg, Tarun Kumar Gupta
2019 J jnl
ONOFIC Pull-Up Approach in Domino Logic Circuits Using FinFET for Subthreshold Leakage Reduction.
Circuits Syst. Signal Process.
Vijay Kumar Magraiya, Tarun Kumar Gupta
2019 J jnl
ONOFIC-based leakage reduction technique for FinFET domino circuits.
Int. J. Circuit Theory Appl.
Vijay Kumar Magraiya, Tarun Kumar Gupta
2019 J jnl
Performance evaluation of single-ended disturb-free CNTFET-based multi-Vt SRAM.
Microelectron. J.
Pramod Kumar Patel, M. M. Malik, Tarun Kumar Gupta
2018 J jnl
Analysis of Noise Immunity for Wide OR Footless Domino Circuit Using Keeper Controlling Network.
Circuits Syst. Signal Process.
Amit Kumar Pandey, Pawan Kumar Verma, Rajesh Verma, Tarun Kumar Gupta
2018 J jnl
New Leakage Reduction Techniques for FinFET Technology with Its Application.
J. Circuits Syst. Comput.
Ajay Kumar Dadoria, Kavita Khare, Tarun Kumar Gupta, R. P. Singh
2018 J jnl
Optimizing Deep Neural Network Architecture: A Tabu Search Based Approach.
CoRR
Tarun Kumar Gupta, Khalid Raza
2015 J jnl
An Improved Fuzzy Voting Scheme for Fault Tolerant Systems.
Int. J. Appl. Evol. Comput.
Ram Murti Rawat, Tarun Kumar Gupta, Mohammad Sajid, Shiv Prakash, Dinesh Prasad Sahu, Sohan Kumar Yadav, Chanchal Kumar
2015 — conf
Comparative Study of Bakhshālī Square Root Method with Newton's Iterative Method.
SocProS (1)
Nidhi Handa, Tarun Kumar Gupta, S. L. Singh
2013 J jnl
Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits.
Circuits Syst. Signal Process.
Tarun Kumar Gupta, Kavita Khare