Tarik Graba

33 papers B 1C 8Journal 9Unranked 15
YearRankTypeTitle / Venue / Authors
2023 — conf
Jitter Compensation Mechanism for Dynamic Deterministic Networks.
OFC
Guillaume Soudais, Tarik Graba, Yves Mathieu, Sébastien Bigo
2021 J jnl
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE.
IEEE Trans. Inf. Forensics Secur.
Ville Yli-Mäyry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma
2021 C conf
RSM Protection of the PRESENT Lightweight Cipher as a RISC-V Extension.
DSD
Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Jean-Luc Danger
2020 J jnl
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression.
IEEE Trans. Computers
Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger
2020 C conf
RISC-V Extension for Lightweight Cryptography.
DSD
Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Jean-Luc Danger
2019 — conf
Classification of Lightweight Block Ciphers for Specific Processor Accelerated Implementations.
ICECS
Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Sylvain Guilley, Jean-Luc Danger
2018 C conf
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology.
DSD
Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata
2018 C conf
Generic Architecture for Lightweight Block Ciphers: A First Step Towards Agile Implementation of Multiple Ciphers.
WISTP
Etienne Tehrani, Jean-Luc Danger, Tarik Graba
2017 J jnl
Cryptographically Secure Shield for Security IPs Protection.
IEEE Trans. Computers
Xuan Thuy Ngo, Jean-Luc Danger, Sylvain Guilley, Tarik Graba, Yves Mathieu, Zakaria Najm, Shivam Bhasin
2017 J jnl
Multi-level formal verification - A new approach against fault injection attack.
J. Cryptogr. Eng.
Laurent Sauvage, Tarik Graba, Thibault Porteboeuf
2016 J jnl
All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition.
IEEE Trans. Circuits Syst. II Express Briefs
Han Le Duc, Duc Minh Nguyen, Chadi Jabbour, Tarik Graba, Patricia Desgreys, Olivier Jamin, Van Tam Nguyen
2016 J jnl
Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology.
CoRR
Sumanta Chaudhuri, Tarik Graba, Yves Mathieu
2015 — conf
Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA.
ICICDT
Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger
2015 C conf
Hardware implementation of all digital calibration for undersampling TIADCs.
ISCAS
Han Le Duc, Duc Minh Nguyen, Chadi Jabbour, Tarik Graba, Patricia Desgreys, Olivier Jamin, Van Tam Nguyen
2015 J jnl
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis.
IET Inf. Secur.
Wei He, Shivam Bhasin, Andrés Otero, Tarik Graba, Eduardo de la Torre, Jean-Luc Danger
2014 — conf
A look into SIMON from a side-channel perspective.
HOST
Shivam Bhasin, Tarik Graba, Jean-Luc Danger, Zakaria Najm
2014 B conf
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security.
FPL
Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez
2014 — conf
Cryptographically secure shields.
HOST
Jean-Michel Cioranesco, Jean-Luc Danger, Tarik Graba, Sylvain Guilley, Yves Mathieu, David Naccache, Xuan Thuy Ngo
2014 — conf
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology.
ES4CPS@DATE
Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata
2014 — conf
Side channel analysis on an embedded hardware fingerprint biometric comparator & low cost countermeasures.
HASP@ISCA
Taoufik Chouta, Tarik Graba, Jean-Luc Danger, Julien Bringer, Maël Berthier, Yves Bocktaels, Mélanie Favre, Hervé Chabanne
2014 — conf
Studying Leakages on an Embedded Biometric System Using Side Channel Analysis.
COSADE
Maël Berthier, Yves Bocktaels, Julien Bringer, Hervé Chabanne, Taoufik Chouta, Jean-Luc Danger, Mélanie Favre, Tarik Graba
2014 J jnl
Studying Potential Side Channel Leakages on an Embedded Biometric Comparison System.
IACR Cryptol. ePrint Arch.
Maël Berthier, Yves Bocktaels, Julien Bringer, Hervé Chabanne, Taoufik Chouta, Jean-Luc Danger, Mélanie Favre, Tarik Graba
2013 — conf
Design methodology of an ASIC TRNG based on an open-loop delay chain.
NEWCAS
Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger, Yves Mathieu
2013 C conf
FPGA Design of an Open-Loop True Random Number Generator.
DSD
Florent Lozach, Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger
2013 — conf
Stochastic Model of a Metastability-Based True Random Number Generator.
TRUST
Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger
2012 C conf
A Small and High-Performance Coprocessor for Fingerprint Match-on-Card.
DSD
Taoufik Chouta, Jean-Luc Danger, Laurent Sauvage, Tarik Graba
2011 — conf
Efficient Dual-Rail Implementations in FPGA Using Block RAMs.
ReConFig
Shivam Bhasin, Sylvain Guilley, Youssef Souissi, Tarik Graba, Jean-Luc Danger
2009 J jnl
A System for an Accurate 3D Reconstruction in Video Endoscopy Capsule.
EURASIP J. Embed. Syst.
Anthony Kolar, Olivier Romain, Jade Ayoub, David Faura, Sylvain Viateur, Bertrand Granado, Tarik Graba
2009 — conf
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow.
ReConFig
Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane
2009 C conf
WDDL is Protected against Setup Time Violation Attacks.
FDTC
Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger
2008 — conf
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs.
SSIRI
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu
2008 — conf
Place-and-Route Impact on the Security of DPL Designs in FPGAs.
HOST
Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong
2006 — conf
An Integrated Digital Architecture for the Real-time Reconstruction in a VSiP Sensor.
ICECS
Anthony Kolar, Tarik Graba, Andréa Pinna, Olivier Romain, Bertrand Granado, Thomas Ea