Tarek Ould-Bachir

23 papers A 1B 2C 4Journal 11Unranked 5
YearRankTypeTitle / Venue / Authors
2026 A conf
Synchronized CPU-FPGA Tracing for Heterogeneous Platforms.
FPGA
Nicolas Deloumeau, Tarek Ould-Bachir, David Evans, Andrew Handke, Jamie Sanderson, François Tetreault
2025 J jnl
A Stateful Extension to P4THLS for Advanced Telemetry and Flow Control.
Future Internet
Mostafa Abbas Mollaei, Tarek Ould-Bachir, Yvon Savaria
2025 J jnl
DA OMS-CNN: Dual-Attention OMS-CNN with 3D Swin Transformer for Early-Stage Lung Cancer Detection.
Informatics
Yadollah Zamanidoost, Matis Rivron, Tarek Ould-Bachir, Sylvain Martel
2025 J jnl
Enhancing CuFP Library with Self-Alignment Technique.
Comput.
Fahimeh Hajizadeh, Tarek Ould-Bachir, Jean-Pierre David
2025 — conf
Improved High-Radix Carry-Save Adders for Low-Latency Vector Reduction on Fpga.
NewCAS
Fahimeh Hajizadeh, Paul-André Bisson, Tarek Ould-Bachir, Jean-Pierre David
2025 J jnl
OMS-CNN: Optimized Multi-Scale CNN for Lung Nodule Detection Based on Faster R-CNN.
IEEE J. Biomed. Health Informatics
Yadollah Zamanidoost, Tarek Ould-Bachir, Sylvain Martel
2025 J jnl
P4THLS: A Templated HLS Framework to Automate Efficient Mapping of P4 Data-Plane Applications to FPGAs.
IEEE Access
Mostafa Abbas Mollaei, Tarek Ould-Bachir, Yvon Savaria
2024 C conf
DMM-ESH Technique for Real-time Simulation of Three-level NPC Dual Active Bridge Converter.
IECON
Zheng Yan, Tarek Ould-Bachir, Karim Meddah, Téo Robert, Romain Monthéard, Emmanuel Rutovic
2024 B conf
Enhancing P4 Syntax to Support Extended Finite State Machines as Native Stateful Objects.
NetSoft
Florent Allard, Tarek Ould-Bachir, Yvon Savaria
2024 J jnl
Innovative Non-Invasive and Non-Intrusive Precision Thermometry in Stainless-Steel Tanks Using Ultrasound Transducers.
Sensors
Ahmed Bouzid, Saad Chidami, Tristan Quentin Lailler, Adrián Carrillo García, Tarek Ould-Bachir, Jamal Chaouki
2024 — conf
Normal and Resilient Mode FPGA-based Access Gateway Function Through P4-generated RTL.
DRCN
Mostafa Abbas Mollaei, Tarek Ould-Bachir, Yvon Savaria
2024 J jnl
PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA.
Future Internet
Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria
2023 C conf
An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs.
ISCAS
Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria
2023 B conf
Efficient Region Proposal Extraction of Small Lung Nodules Using Enhanced VGG16 Network Model.
CBMS
Yadollah Zamanidoost, Nada Alami-Chentoufi, Tarek Ould-Bachir, Sylvain Martel
2023 — conf
Implementing and Evaluating a P4-based Access Gateway Function on a Tofino Switch.
CommNet
El-Mehdi Makhroute, Mohammed-Ayoub Elharti, Vincent Brouillard, Yvon Savaria, Tarek Ould-Bachir
2022 C conf
A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing.
ISCAS
Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria
2019 — conf
A Low-Latency Reconfigurable Multistage Interconnection Network.
CCECE
Federico Montano, Tarek Ould-Bachir, Jean Mahseredjian, Jean-Pierre David
2018 J jnl
An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters.
IEEE Trans. Ind. Electron.
Federico Montano, Tarek Ould-Bachir, Jean-Pierre David
2013 J jnl
A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits.
Math. Comput. Simul.
Tarek Ould-Bachir, Christian Dufour, Jean Bélanger, Jean Mahseredjian, Jean-Pierre David
2013 J jnl
Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators.
ACM Trans. Reconfigurable Technol. Syst.
Tarek Ould-Bachir, Jean-Pierre David
2012 J jnl
A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters.
IEEE Trans. Ind. Electron.
Hugo Fortin-Blanchette, Tarek Ould-Bachir, Jean-Pierre David
2012 — conf
Effective floating-point calculation engines intended for the FPGA-based HIL simulation.
ISIE
Tarek Ould-Bachir, Christian Dufour, Jean Bélanger, Jean Mahseredjian, Jean-Pierre David
2012 C conf
General-purpose reconfigurable low-latency electric circuit and motor drive solver on FPGA.
IECON
Christian Dufour, Sébastien Cense, Tarek Ould-Bachir, Luc-André Grégoire, Jean Bélanger