Tapan J. Chakraborty

27 papers A* 3A 7C 1Misc 5Journal 7Unranked 4
YearRankTypeTitle / Venue / Authors
2013 C conf
Functional Fmax test-time reduction using novel DFTs for circuit initialization.
ICCD
Ujjwal Guin, Tapan J. Chakraborty, Mohammad Tehranipoor
2010 J jnl
A Common Language Framework for Next-Generation Embedded Testing.
IEEE Des. Test Comput.
Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook
2008 A conf
A New Language Approach for IJTAG.
ITC
Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook
2008 Misc conf
A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits.
VLSI Design
Aditya Jagirdar, Roystein Oliveira, Tapan J. Chakraborty
2007 — conf
A TMR Scheme for SEU Mitigation in Scan Flip-Flops.
ISQED
Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty
2007 A conf
A practical approach to comprehensive system test & debug using boundary scan based test architecture.
ITC
Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren
2007 — conf
FPGA Prototyping of a Scan Based System-On-Chip Design.
ReCoSoC
Brendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook
2005 — conf
Efficient Test Architecture based on Boundary Scan for Comprehensive System Test.
Asian Test Symposium
Tapan J. Chakraborty
2002 A conf
A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur.
ITC
Tapan J. Chakraborty, Chen-Huan Chiang
2000 J jnl
Improving path delay testability of sequential circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
2000 J jnl
Path delay fault simulation of sequential circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
1999 J jnl
Built in self test: a complete test solution for telecommunication systems.
IEEE Commun. Mag.
Nilanjan Mukherjee, Tapan J. Chakraborty, Ramesh Karri
1998 A conf
A BIST scheme for the detection of path-delay faults.
ITC
Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik
1997 A conf
Effective Path Selection for Delay Fault Testing of Sequential Circuits.
ITC
Tapan J. Chakraborty, Vishwani D. Agrawal
1997 J jnl
On variable clock methods for path delay testing of sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
1996 Misc conf
Design for high-speed testability of stuck-at faults.
VLSI Design
Tapan J. Chakraborty, Vishwani D. Agrawal
1995 A conf
High-Performance Circuit Testing with Slow-Speed Testers.
ITC
Vishwani D. Agrawal, Tapan J. Chakraborty
1995 Misc conf
Robust testing for stuck-at faults.
VLSI Design
Tapan J. Chakraborty, Vishwani D. Agrawal
1995 Misc conf
Simulation of at-speed tests for stuck-at faults.
VTS
Tapan J. Chakraborty, Vishwani D. Agrawal
1994 — conf
Delay independent initialization of sequential circuits.
Great Lakes Symposium on VLSI
Tapan J. Chakraborty, Vishwani D. Agrawal
1993 A* conf
Design for Testability for Path Delay faults in Sequential Circuits.
DAC
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
1993 Misc conf
Partial scan testing with single clock control.
VTS
Vishwani D. Agrawal, Tapan J. Chakraborty
1992 A* conf
Delay Fault Models and Test Generation for Random Logic Sequential Circuits.
DAC
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
1991 A* conf
Enhanced Controllability for
DAC
Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin
1991 J jnl
On behavior fault modeling for digital designs.
J. Electron. Test.
Sumit Ghosh, Tapan J. Chakraborty
1989 J jnl
Gentest: An Automatic Test-Generation System for Sequential Circuits.
Computer
Wu-Tung Cheng, Tapan J. Chakraborty
1988 A conf
On Behavior Fault Modeling for Combinational Digital Designs.
ITC
Tapan J. Chakraborty, Sumit Ghosh