Tanay Karnik - RankMe

96 papers A* 8A 14B 1C 2Misc 1Journal 33Unranked 36

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Standardized 20-Tb/s Bandwidth Scalable Heterogeneous 2.5-D System Supporting Assembly Time Workload-Dependent Chiplet Configurations. IEEE J. Solid State Circuits Srivatsa Rangachar Srinivasa, Dileep John Kurian, Paolo A. Aseron, Prerna Budhkar, Vinayak Honkote, Dan Lake, Mikhail J. Moiseev, Robert J. Munoz, Anuradha Srinivasan, Tanay Karnik
2025	—	`conf`	A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations. ISSCC Srivatsa Rangachar Srinivasa, Dileep Kurian, Paolo A. Aseron, Prerna Budhkar, Arun Radhakrishnan, Alejandro Cardenas Lopez, Jainaveen Sundaram, Vinayak Honkote, Leonid Azarenkov, Dan Lake, Jaykant Timbadiya, Mikhail J. Moiseev, Brando Perez Esparza, Ronald Kalim, Erika Ramirez Lozano, Mukesh Bhartiya, Sriram Muthukumar, Satish Yada, Sureshbabu Kadavakollu, Saransh Chhabra, Kamakhya Prasad Sahu, James Greensky, Xavier Brun, Esdras Juarez Hernandez, Robert Munoz, Thomas P. Thomas, Shawna Liff, Vivek De, Anuradha Srinivasan, Tanay Karnik
2025	—	`conf`	A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System. CICC Srivatsa Rangachar Srinivasa, Prerna Budhkar, Gauthaman Murali, Vui Seng Chua, Paolo A. Aseron, Vinayak Honkote, Ravi R. Iyer, Nilesh Jain, Dileep John Kurian, Anuradha Srinivasan, Tanay Karnik
2025	—	`conf`	A High-Performance Passive Base System for Distributed AI/Media Acceleration. CICC Ragh Kuttappa, Jainaveen Sundaram, Srivatsa Rangachar Srinivasa, Paolo A. Aseron, Gauthaman Murali, Vinayak Honkote, Prerna Budhkar, Dileep Kurian, Ronald Kalim, Thomas P. Thomas, Anuradha Srinivasan, Tanay Karnik
2025	J	`jnl`	A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology. IEEE Solid State Circuits Lett. Ragh Kuttappa, Vinayak Honkote, Amreesh Rao, Gaurav Kamalkar, Kailash Chandrashekar, Eric Finley, Chaitanya Sankuratri, Faran Rafiq, Robert Orton, Nils Hernandez, Anuradha Srinivasan, Tanay Karnik
2025	A	`conf`	Invited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D Integration. ICCAD Gauthaman Murali, Mudit Bhargava, Shairfe Salahuddin, Zhichao Chen, Archana Pandey, Srivatsa Rangachar Srinivasa, Prerna Budhkar, Ragh Kuttappa, Vinayak Honkote, Prashanth Sakthi, Myung-Hee Na, Tanay Karnik
2025	—	`conf`	System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution. ACM Great Lakes Symposium on VLSI Srivatsa Rangachar Srinivasa, Dileep Kurian, Paolo A. Aseron, Prerna Budhkar, Vinayak Honkote, Dan Lake, Jaykant Timbadiya, Satish Yada, Suresh Kadavakollu, James Greensky, Gauthaman Murali, Anuradha Srinivasan, Ragh Kuttappa, Tanay Karnik
2024	—	`conf`	A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems. VLSI Technology and Circuits Vinayak Honkote, Ragh Kuttappa, Jainaveen Sundaram, Satish Yada, Chinnusamy Kalimuthu, Juhi Patil, Richard Lee, Cristan Paulino, Paolo A. Aseron, Trang Nguyen, Amreesh Rao, Dileep Kurian, Mingming Xu, Yan Song, Tanay Karnik, Anuradha Srinivasan, Vivek De
2023	B	`conf`	CPU Microarchitectural Performance Analysis of SVT-AV1 Encoder. ICIP Prerna Budhkar, Navneet Rao, Jainaveen Sundaram, Tanay Karnik
2023	J	`jnl`	On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. Gauthaman Murali, Aditya Iyer, Lingjun Zhu, Jianming Tong, Francisco Muñoz-Martínez, Srivatsa Rangachar Srinivasa, Tanay Karnik, Tushar Krishna, Sung Kyu Lim
2022	—	`conf`	Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems. ISQED Srivatsa Rangachar Srinivasa, Jainaveen Sundaram Priya, Dileep Kurian, Erika Ramirez Lozano, Satish Yada, Saransh Chhabra, Kamakhya Prasad Sahu, Paolo A. Aseron, Ronald Kalim, Anuradha Srinivasan, Tanay Karnik
2022	—	`conf`	Innovations for Intelligent Edge. ESSCIRC Vida Ilderem, Stefano Pellerano, Jim Tschanz, Tanay Karnik, Vivek De
2022	J	`jnl`	Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Amir Amirkhany, Tanay Karnik, Shidhartha Das, Jun Deguchi, Yasuhiko Taito
2022	—	`conf`	Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration. ISPD Tanay Karnik
2022	C	`conf`	Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer. ISCAS Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, Anuradha Srinivasan
2021	A	`conf`	A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding. DATE Jainaveen Sundaram, Srivatsa Rangachar Srinivasa, Dileep Kurian, Indranil Chakraborty, Sirisha Rani Kale, Nilesh Jain, Tanay Karnik, Ravi R. Iyer, Anuradha Srinivasan
2021	—	`conf`	F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors. ISSCC Sukhwan Lim, Yongpan Liu, Luca Benini, Tanay Karnik, Hsie-Chia Chang
2021	—	`conf`	Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration (Invited). SLIP Tanay Karnik
2021	—	`conf`	Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation. ISQED Srivatsa Srinivasa, Akshay Krishna Ramanathan, Jainaveen Sundaram, Dileep Kurian, Srinivasan Gopal, Nilesh Jain, Anuradha Srinivasan, Ravi R. Iyer, Vijaykrishnan Narayanan, Tanay Karnik
2020	—	`conf`	Self-Powered IOT System for Edge Inference. ISQED Dileep Kurian, Tanay Karnik, Saksham Soni, Saransh Chhabra, Suhwan Kim, Jaykant Timbadiya, Ankit Gupta, Krishnan Ravichandran, Mukesh Bhartiya, Angela Nicoara
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019	—	`conf`	Hierarchical Design Methodology and Optimization for Proximity Communication based Contactless 3D ThruChip Interface. 3DIC Srinivasan Gopal, Deukhyoun Heo, Tanay Karnik
2018	—	`conf`	A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes. VLSI Circuits Suhwan Kim, Vaibhav A. Vaidya, Christopher Schaef, Andrew Lines, Harish Krishnamurthy, Sheldon Weng, Xiaosen Liu, Dileep Kurian, Tanay Karnik, Krishnan Ravichandran, James W. Tschanz, Vivek De
2018	—	`conf`	A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. ISSCC Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav A. Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De
2018	A*	`conf`	Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems. DAC Lavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney, Tanay Karnik, Hong Wang
2018	A*	`conf`	Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache. ISCA Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Steven Swanson, Ian Young, Hong Wang
2018	J	`jnl`	Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms. IEEE J. Emerg. Sel. Topics Circuits Syst. Arindam Basu, Meng-Fan Chang, Elisabetta Chicca, Tanay Karnik, Hai Helen Li, Jae-sun Seo
2018	J	`jnl`	Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions. IEEE J. Emerg. Sel. Topics Circuits Syst. Arindam Basu, Jyotibdha Acharya, Tanay Karnik, Huichu Liu, Hai Helen Li, Jae-sun Seo, Chang Song
2018	—	`conf`	Technology trends, requirements and challenges for ubiquitous self-powered IOT systems deployment. IGSC Tanay Karnik
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2015	J	`jnl`	Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design. ACM J. Emerg. Technol. Comput. Syst. Vivek K. De, Andrew B. Kahng, Tanay Karnik, Bao Liu, Milad Maleki, Lu Wang
2014	A	`ed.`	International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014 ISLPED Yuan Xie, Tanay Karnik, Muhammad M. Khellah, Renu Mehra
2014	—	`conf`	Resiliency for many-core system on a chip. ASP-DAC Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar
2013	J	`jnl`	A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance. IEEE J. Solid State Circuits Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, James W. Tschanz
2013	J	`jnl`	Adaptive and Resilient Circuits for Dynamic Variation Tolerance. IEEE Des. Test Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Tanay Karnik, Vivek K. De
2013	—	`conf`	F5: Frequency generation and clock distribution. ISSCC Antonio Liscidini, SeongHwan Cho, Tony Chan Carusone, Tanay Karnik, Mike Keaveney, Brian Otis, Aaron Partridge, Christoph Sandner
2013	A	`ed.`	International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 2013 ISLPED Pai H. Chou, Ru Huang, Yuan Xie, Tanay Karnik
2013	A*	`conf`	Power management and delivery for high-performance microprocessors. DAC Tanay Karnik, Mondira (Mandy) Deb Pant, Shekhar Borkar
2012	—	`conf`	A 22nm dynamically adaptive clock distribution for voltage droop tolerance. VLSIC Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz
2012	—	`conf`	Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. ISSCC Jaydeep P. Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah, James W. Tschanz, Vivek De
2012	A	`conf`	Design for test and reliability in ultimate CMOS. DATE Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky
2012	J	`jnl`	Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu
2012	A	`conf`	Scaling the "Memory Wall": Designer track. ICCAD Shih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held
2011	—	`conf`	3DICs for tera-scale computing: a case study. ISPD Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar
2011	J	`jnl`	A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De
2011	J	`jnl`	All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De
2011	—	`conf`	Coordinating 3D designs: Interface IP, standards or free form? 3DIC Paul D. Franzon, W. Rhett Davis, Zheng Zhou, Shivam Priyadarshi, Matthew Hogan, Tanay Karnik, Ganapati Srinavasa
2011	J	`jnl`	Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2011	—	`conf`	Integrated inductors with magnetic materials for on-chip power conversion. Hot Chips Symposium Donald S. Gardner, Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Shekhar Borkar
2011	J	`jnl`	Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. IET Comput. Digit. Tech. Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar
2011	J	`jnl`	Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. IEEE J. Solid State Circuits Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De
2010	—	`conf`	A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2010	—	`conf`	Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De
2010	J	`jnl`	Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. IEEE J. Solid State Circuits Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang
2010	—	`conf`	Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays. CICC Bibiche M. Geuskens, Muhammad M. Khellah, Jaydeep P. Kulkarni, Tanay Karnik, Vivek De
2010	—	`conf`	PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep P. Kulkarni, James W. Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah
2010	—	`conf`	Resilient design in scaled CMOS for energy efficiency. ASP-DAC James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep P. Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De
2010	A	`conf`	Resilient microprocessor design for high performance & energy efficiency. ISLPED Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2009	J	`jnl`	2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi
2009	J	`jnl`	A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters. IEEE J. Solid State Circuits Pengfei Li, Lin Xue, Peter Hazucha, Tanay Karnik, Rizwan Bashirullah
2009	A*	`conf`	Circuit techniques for dynamic variation tolerance. DAC Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar
2009	J	`jnl`	Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. IEEE J. Solid State Circuits Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De
2009	J	`jnl`	Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. IEEE J. Solid State Circuits Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De
2009	A	`conf`	Resilient circuits - Enabling energy-efficient performance and reliability. ICCAD James W. Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik
2009	J	`jnl`	SRAM dynamic stability estimation using MPFP and its applications. Microelectron. J. DiaaEldin Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek De
2008	—	`conf`	2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi
2008	J	`jnl`	A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction. IEEE J. Solid State Circuits Jianping Xu, Peter Hazucha, Zuoguo Wu, Paolo A. Aseron, Mingwei Huang, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Vivek De, Tanay Karnik, Greg Taylor
2008	J	`jnl`	Accurate Estimation of SRAM Dynamic Stability. IEEE Trans. Very Large Scale Integr. Syst. D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De
2008	—	`conf`	Analytical Model for the Propagation Delay of Through Silicon Vias. ISQED DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De
2008	—	`conf`	Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance. ISSCC Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De
2008	J	`jnl`	Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power. IEEE Trans. Very Large Scale Integr. Syst. Hao Yu, Yiyu Shi, Lei He, Tanay Karnik
2007	—	`conf`	Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. ISSCC James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De
2007	J	`jnl`	High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters. IEEE J. Solid State Circuits Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Saravanan Rajapandian, Tanay Karnik
2007	—	`conf`	Low Voltage Buffered Bandgap Reference. ISQED Peter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner, Kenneth Ikeda, Gell Gellman, Tanay Karnik
2007	—	`conf`	On-Die Supply-Resonance Suppression Using Band-Limited Active Damping. ISSCC Jianping Xu, Peter Hazucha, Mingwei Huang, Paolo A. Aseron, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Cangsang Zhao, Vivek De, Tanay Karnik, Greg Taylor
2006	—	`conf`	A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters. ISSCC Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Saravanan Rajapandian, Tanay Karnik
2006	C	`conf`	High-frequency DC-DC conversion : fact or fiction. ISCAS Tanay Karnik, Peter Hazucha, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner
2006	J	`jnl`	High-voltage power delivery through charge recycling. IEEE J. Solid State Circuits Saravanan Rajapandian, Kenneth L. Shepard, Peter Hazucha, Tanay Karnik
2006	A	`conf`	Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. ISLPED Changbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He, Tanay Karnik
2006	Misc	`conf`	Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. VLSI Design Ruchir Puri, Tanay Karnik, Rajiv V. Joshi
2006	A	`conf`	Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. ISLPED Hao Yu, Yiyu Shi, Lei He, Tanay Karnik
2005	J	`jnl`	A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. IEEE J. Solid State Circuits Peter Hazucha, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Paul Hack, Gregory E. Dermer, Siva G. Narendra, Donald S. Gardner, Tanay Karnik, Vivek De, Shekhar Borkar
2005	J	`jnl`	Area-efficient linear regulator with ultra-fast load regulation. IEEE J. Solid State Circuits Peter Hazucha, Tanay Karnik, Bradley A. Bloechel, Colleen Parsons, David Finan, Shekhar Borkar
2005	—	`conf`	Design of sub-90nm Circuits and Design Methodologies. ISQED Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi
2005	A*	`conf`	Logic soft errors in sub-65nm technologies design and CAD challenges. DAC Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang
2004	J	`jnl`	Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes. IEEE Trans. Dependable Secur. Comput. Tanay Karnik, Peter Hazucha, Jagdish Patel
2004	A*	`conf`	Design and reliability challenges in nanometer technologies. DAC Shekhar Borkar, Tanay Karnik, Vivek De
2004	A	`conf`	Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. ISLPED Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva G. Narendra, Tanay Karnik, Vivek De
2004	A	`conf`	HiSIM: hierarchical interconnect-centric circuit simulator. ICCAD Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik
2004	J	`jnl`	Measurements and analysis of SER-tolerant latch in a 90-nm dual-V IEEE J. Solid State Circuits Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
2003	A*	`conf`	Parameter variations and impact on circuits and microarchitecture. DAC Shekhar Borkar, Tanay Karnik, Siva G. Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De
2002	A	`conf`	Sub-90nm technologies: challenges and opportunities for CAD. ICCAD Tanay Karnik, Shekhar Borkar, Vivek De
2002	A*	`conf`	Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
1999	—	`ch.`	Microprocessor Layout Method. The VLSI Handbook Tanay Karnik
1995	A	`conf`	An empirical model for accurate estimation of routing delay in FPGAs. ICCAD Tanay Karnik, Sung-Mo Kang
1994	J	`jnl`	Structural and behavioral synthesis for testability techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab