Tan-Li Chou

20 papers A 3C 1Misc 1Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2026 — conf
15.4 A 16nm 168Mb Embedded STT-MRAM with 0.0249µm
ISSCC
Po-Hao Lee, Chia-Fu Lee, Hon-Jarn Lin, Cheng-Han Lu, Yen-An Chang, Pranata W. Sanjaya, Chia-Jung Tsen, Kuan-Chun Chen, Ming-Chieh Lin, Chao-Jung Hung, Tan-Li Chou, Chih-Hui Weng, Chia-Yu Wang, J. J. Wu, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang
2026 J jnl
A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm
IEEE J. Solid State Circuits
Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Kinshuk Khare, Brian Crafton, Hiroaki Ishii, Cheng-En Lee, Xiaochen Peng, Xiaoyu Sun, Yorinobu Fujino, Chia-Jung Tsen, Vineet Joshi, Chao-Kai Chuang, Takeshi Hashizume, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Hidehiro Fujiwara, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2024 — conf
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm
ISSCC
Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2023 — conf
A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.
ISSCC
Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Yen-An Chang, Cheng-Han Lu, Yu-Lin Chen, Chieh-Pu Lo, Chung-Chieh Chen, Cheng-Hsiung Kuo, Tan-Li Chou, Chia-Yu Wang, J. J. Wu, Roger Wang, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang
2023 — conf
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update.
ISSCC
Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2022 — conf
A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications.
VLSI Technology and Circuits
Chia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, Haruki Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan-Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang
2022 — conf
A 5-nm 254-TOPS/W 221-TOPS/mm
ISSCC
Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2021 — conf
An 89TOPS/W and 16.3TOPS/mm
ISSCC
Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Cheng Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang
2001 — conf
Integrated power supply planning and floorplanning.
ASP-DAC
I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong
2000 J jnl
Estimating Circuit Activity in Combinational CMOS Digital Circuits.
IEEE Des. Test Comput.
Hendrawan Soeleman, Kaushik Roy, Tan-Li Chou
2000 — conf
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion.
ISPD
I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong
1998 J jnl
Efficient statistical approach to estimate power considering uncertain properties of primary inputs.
IEEE Trans. Very Large Scale Integr. Syst.
Zhanping Chen, Kaushik Roy, Tan-Li Chou
1998 J jnl
Power Estimation Under Uncertain Delays.
Integr. Comput. Aided Eng.
Tan-Li Chou, Kaushik Roy
1997 Misc conf
Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique.
VLSI Design
Priya Patil, Tan-Li Chou, Kaushik Roy, Rabindra Roy
1997 A conf
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs.
ICCAD
Zhanping Chen, Kaushik Roy, Tan-Li Chou
1996 J jnl
Accurate power estimation of CMOS sequential circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Tan-Li Chou, Kaushik Roy
1996 J jnl
Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tan-Li Chou, Kaushik Roy
1995 C conf
Estimation of sequential circuit activity considering spatial and temporal correlations.
ICCD
Tan-Li Chou, Kaushik Roy
1995 A conf
Statistical estimation of sequential circuit activity.
ICCAD
Tan-Li Chou, Kaushik Roy
1994 A conf
Estimation of circuit activity considering signal correlations and simultaneous switching.
ICCAD
Tan-Li Chou, Kaushik Roy, Sharat Prasad