Tameesh Suri

11 papers A* 1B 1Misc 3Journal 3Unranked 3
YearRankTypeTitle / Venue / Authors
2017 — conf
Adaptive and Scalable Predictive Page Policies for High Core-Count Server CPUs.
ARCS
Tameesh Suri, Aneesh Aggarwal
2015 A* conf
Performance Characterization of Hyperscale Applicationson on NVMe SSDs.
SIGMETRICS
Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan
2015 Misc conf
Performance analysis of NVMe SSDs and their implication on real world databases.
SYSTOR
Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Tameesh Suri, Manu Awasthi, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan
2015 B conf
System-Level Characterization of Datacenter Applications.
ICPE
Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Mrinmoy Ghosh, Vijay Balakrishnan
2014 J jnl
SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors.
IEEE Trans. Computers
Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Tameesh Suri
2011 — conf
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors.
Conf. Computing Frontiers
Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Tameesh Suri
2010 J jnl
Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration.
Int. J. Parallel Program.
Tameesh Suri, Aneesh Aggarwal
2009 Misc conf
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration.
VLSI Design
Tameesh Suri, Aneesh Aggarwal
2009 — conf
Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration.
Conf. Computing Frontiers
Tameesh Suri, Aneesh Aggarwal
2008 Misc conf
Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware.
HiPC
Tameesh Suri, Aneesh Aggarwal
2007 J jnl
Improving instruction level parallelism through reconfigurable units in superscalar processors.
SIGARCH Comput. Archit. News
Tameesh Suri