Tali Moreshet

26 papers A* 1A 2B 4Misc 2Journal 7Unranked 10
YearRankTypeTitle / Venue / Authors
2022 B conf
HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures.
SPAA
Jiwon Choe, Andrew Crotty, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
2022 — conf
Towards Hardware Accelerated Garbage Collection with Near-Memory Processing.
HPEC
Samuel Thomas, Jiwon Choe, Ofir Gordon, Erez Petrank, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
2020 J jnl
Voltage Noise Mitigation With Barrier Approximation.
IEEE Comput. Archit. Lett.
Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu
2019 — conf
Attacking memory-hard scrypt with near-data-processing.
MEMSYS
Jiwon Choe, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2019 — conf
Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis.
IISWC
Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu
2019 B conf
Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation.
SPAA
Jiwon Choe, Amy Huang, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
2019 A conf
IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM.
DATE
Dimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar
2018 J jnl
Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures.
Int. J. Parallel Program.
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar
2017 J jnl
Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency.
ACM Trans. Embed. Comput. Syst.
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
2017 — conf
Evaluating critical bits in arithmetic operations due to timing violations.
HPEC
Sungseob Whang, Tymani Rachford, Dimitra Papagiannopoulou, Tali Moreshet, R. Iris Bahar
2016 Misc conf
Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems.
CASES
Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar
2015 J jnl
Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems.
ACM Trans. Embed. Comput. Syst.
Dimitra Papagiannopoulou, Giuseppe Capodanno, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
2015 — conf
Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution.
ACM Great Lakes Symposium on VLSI
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar
2014 — conf
Speculative synchronization for coherence-free embedded NUMA architectures.
ICSAMOS
Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar
2013 — conf
Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs.
MES
Dimitra Papagiannopoulou, R. Iris Bahar, Tali Moreshet, Maurice Herlihy, Andrea Marongiu, Luca Benini
2011 B conf
Power-Performance Comparison of Single-Task Driven Many-Cores.
ICPADS
Fuat Keceli, Tali Moreshet, Uzi Vishkin
2011 Misc conf
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs.
CODES+ISSS
Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R. Iris Bahar, Tali Moreshet, Luca Benini, Maurice Herlihy
2010 J jnl
Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems.
J. Parallel Distributed Comput.
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2010 — conf
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems.
HiPEAC
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2010 — conf
Thermal Management of a Many-Core Processor under Fine-Grained Parallelism.
Euro-Par Workshops (1)
Fuat Keceli, Tali Moreshet, Uzi Vishkin
2008 — conf
Energy efficient synchronization techniques for embedded architectures.
ACM Great Lakes Symposium on VLSI
Cesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2007 J jnl
A hardware/software framework for supporting transactional memory in a MPSoC environment.
SIGARCH Comput. Archit. News
Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy
2006 B conf
Energy implications of multiprocessor synchronization.
SPAA
Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2005 A conf
Energy reduction in multiprocessor systems using transactional memory.
ISLPED
Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2004 J jnl
Effects of speculation on performance and issue queue design.
IEEE Trans. Very Large Scale Integr. Syst.
Tali Moreshet, R. Iris Bahar
2003 A* conf
Power-aware issue queue design for speculative instructions.
DAC
Tali Moreshet, R. Iris Bahar