Takuya Saraya

16 papers C 1Journal 2Unranked 13
YearRankTypeTitle / Venue / Authors
2025 — conf
A Study on the Origin of MOSFET Random Telegraph Noise Under Strong Inversion at Cryogenic Temperatures.
IRPS
Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Hiroshi Oka, Takahiro Mori, Shinichi Takagi, Masaharu Kobayashi, Toshiro Hiramoto
2024 — conf
Performance and Reliability of Nanosheet Oxide Semiconductor FETs with ALD-Grown InGaO for 3D Integration (Invited).
IRPS
Masaharu Kobayashi, Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka
2024 — conf
Scaling Potential of Nanosheet Oxide Semiconductor FETs for Monolithic 3D Integration-ALD Material Engineering, High-Field Transport, Statistical Variability.
VLSI Technology and Circuits
Kaito Hikake, Xingyu Huang, Sung-Hun Kim, Kota Sakai, Zhuo Li, Tomoko Mizutani, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi
2023 — conf
A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices.
VLSI Technology and Circuits
Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi
2022 — conf
3-Layer stacked pixel-parallel CMOS image sensors using hybrid bonding of SOI wafers.
Imaging Sensors and Systems
Masahide Goto, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto
2021 — conf
Recent Progress of Double/Dual-Gate Silicon IGBT Technologies.
ASICON
Toshiro Hiramoto, Takuya Saraya
2019 — conf
Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method.
NVMTS
Fei Mo, Yusaku Tagawa, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi
2019 — conf
Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers.
3DIC
Masahide Goto, Joeri De Vos, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Eiji Higurashi, Yuki Honda, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Toshiro Hiramoto
2018 — conf
New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment.
VLSI Circuits
Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Iwai
2018 C conf
Quarter Video Graphics Array Full-Digital Image Sensing with Wide Dynamic Range and Linear Output Using Pixel-Wise 3D Integration.
ISCAS
Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto
2018 — conf
Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately.
ESSDERC
Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Masahiro Watanabe, Naoyuki Shigvo, Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Lwai
2017 — conf
3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat).
ASICON
Kazuo Tsutsui, Kuniyuki Kakushima, Takuya Hoshii, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, Iriya Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, Masaharu Kobayashi, T. Takakura, Toshiro Hiramoto, Atsushi Ogura, Y. Numasawa, Ichiro Omura, Hiromichi Ohashi, Hiroshi Iwai
2015 — conf
Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers.
3DIC
Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto
2013 J jnl
Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress.
IEICE Trans. Electron.
Toshiro Hiramoto, Anil Kumar, Takuya Saraya, Shinji Miyano
2013 J jnl
NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM.
IEICE Trans. Electron.
Nurul Ezaila Alias, Anil Kumar, Takuya Saraya, Shinji Miyano, Toshiro Hiramoto
2011 — conf
Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs.
CICC
Toshiro Hiramoto, Anil Kumar, Tomoko Mizutani, Jun Nishimura, Takuya Saraya