Takuji Miki - RankMe

38 papers C 2Journal 15Unranked 21

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A 20-GHz Low-Noise RF Pulse Generator for Silicon Quantum Computer with 137.4-fs Jitter. IEICE Trans. Electron. Takayasu Norimatsu, Yusuke Wachi, Takuji Miki, Yusuke Kanno, Ryozo Takahashi, Takashi Ogawa, Takeru Utsugi, Tomonori Sekiguchi, Makoto Nagata, Hiroyuki Mizuno
2025	—	`conf`	Cryo-CMOS Analog Circuits for Spin Qubit Control. ASP-DAC Takuji Miki
2025	J	`jnl`	Cryogenic CMOS Analog Circuits and Chip Packaging Techniques towards Large-Scale Silicon Quantum Computers. IEICE Trans. Electron. Takuji Miki, Misato Taguchi, Makoto Nagata
2024	—	`conf`	A Hybrid Simulation Approach for Accurate and Fast System-Level Side-Channel Leakage Evaluation. AsianHOST Kazuki Monta, Takafumi Oki, Rikuu Hasegawa, Takuya Wadatsumi, Takuji Miki, Makoto Nagata, Lang Lin, Norman Chang
2024	—	`conf`	A cryogenic pulse shaper for spin qubit control utilizing 1ns-time-resolution ADCs on an active silicon interposer operating at sub-100 mK temperatures. A-SSCC Ryozo Takahashi, Yusuke Kanno, Takuji Miki, Nobuhiro Kusuno, Hiroyuki Mizuno, Makoto Nagata
2024	C	`conf`	Fault Injection Attacks Exploiting High Voltage Pulsing over Si-Substrate Backside of IC chips. FDTC Yusuke Hayashi, Rikuu Hasegawa, Takuya Wadatsumi, Kazuki Monta, Takuji Miki, Makoto Nagata
2024	—	`conf`	Modeling and Analysis of On-Chip Voltage Fluctuations Caused by Electromagnetic Fault Injection. EMC Compo Takuya Wadatsumi, Rikuu Hasegawa, Kazuki Monta, Takuji Miki, Lang Lin, Norman Chang, Makoto Nagata
2024	—	`conf`	On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injection. COSADE Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata
2024	—	`conf`	Si-Backside Side-Channel Leakage Measurement and Simulation. ISOCC Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata, Lang Lin, Akhilesh Kumar, Norman Chang
2024	—	`conf`	Thermal Flow Simuation and Measurements of 3D Si Chip Stacks with TSVs. 3DIC Shuhei Yokota, Rikuu Hasegawa, Kazuki Monta, Takaaki Okidono, Takuji Miki, Makoto Nagata
2023	—	`conf`	A 13-bit Radiation-Hardened SAR-ADC with Error Correction by Adaptive Topology Transformation. IRPS Yuya Aoki, Tatsuya Iwata, Takuji Miki, Kazutoshi Kobayashi, Takefumi Yoshikawa
2023	—	`conf`	A Triturated Sensing System. ISSCC Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata
2023	J	`jnl`	An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique. IEICE Trans. Electron. Ryozo Takahashi, Takuji Miki, Makoto Nagata
2023	—	`conf`	Characterization of Backside ESD Impacts on Integrated Circuits. IRPS Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kazuki Monta, Takuji Miki, Makoto Nagata
2023	J	`jnl`	Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging. IEICE Trans. Electron. Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo, Takuji Miki, Makoto Nagata
2022	J	`jnl`	An 11-bit 0.008mm IEICE Electron. Express Takuji Miki, Ryozo Takahashi, Makoto Nagata
2022	J	`jnl`	Physical Attack Protection Techniques for IC Chip Level Hardware Security. IEEE Trans. Very Large Scale Integr. Syst. Makoto Nagata, Takuji Miki, Noriyuki Miura
2022	J	`jnl`	Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements. IEEE Des. Test Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Takuji Miki, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen
2022	—	`conf`	Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging. IRPS Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Takuji Miki, Makoto Nagata, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo
2020	J	`jnl`	A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack. IEEE Trans. Circuits Syst. II Express Briefs Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata
2020	C	`conf`	A Random Interrupt Dithering SAR Technique for Secure ADC against Reference-Charge Side-Channel Attack. ISCAS Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata
2020	J	`jnl`	Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2019	J	`jnl`	A 0.72pJ/bit 400μm IEICE Trans. Electron. Takuji Miki, Noriyuki Miura, Makoto Nagata
2019	—	`conf`	A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2019	—	`conf`	On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper. CICC Makoto Nagata, Takuji Miki, Noriyuki Miura
2019	—	`conf`	Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2017	J	`jnl`	A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC. IEEE J. Solid State Circuits Takuji Miki, Toshiaki Ozeki, Jun-ichi Naka
2017	J	`jnl`	A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. IEICE Trans. Electron. Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
2016	—	`conf`	A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC. A-SSCC Takuji Miki, Toshiaki Ozeki, Jun-ichi Naka
2016	—	`conf`	A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. ESSCIRC Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
2016	—	`conf`	A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect. VLSI Circuits Koji Obata, Kazuo Matsukawa, Takuji Miki, Yusuke Tsukamoto, Koji Sushihara
2015	J	`jnl`	A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. IEEE J. Solid State Circuits Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata
2015	J	`jnl`	A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques. IEEE J. Solid State Circuits Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho
2014	—	`conf`	12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. ISSCC Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata
2013	—	`conf`	A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise. ISSCC Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho
2012	J	`jnl`	An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects. IEEE J. Solid State Circuits Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho
2009	—	`conf`	Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. ASP-DAC Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho
2006	—	`conf`	Configurable multi-processor architecture and its processor element design. ASP-DAC Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura, Yuki Matsumoto, Masatsugu Kobayashi, Toshiyuki Kato, Tsutomu Eda, Hironori Yamauchi