Takeshi Ueno

19 papers C 2Journal 12Unranked 5
YearRankTypeTitle / Venue / Authors
2023 J jnl
An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs.
IEEE J. Solid State Circuits
Shusuke Kawai, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka
2019 — conf
A 4.5V/ns Active Slew-Rate-Controlling Gate Driver with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs.
ISSCC
Shusuke Kawai, Takeshi Ueno, Kohei Onizuka
2016 — conf
20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvesting.
A-SSCC
Yosuke Toyama, Taichi Ogawa, Takeshi Ueno, Tetsuro Itakura
2012 J jnl
Modeling Patent Quality: A System for Large-scale Patentability Analysis using Text Mining.
Inf. Media Technol.
Shohei Hido, Shoko Suzuki, Risa Nishiyama, Takashi Imamichi, Rikiya Takahashi, Tetsuya Nasukawa, Tsuyoshi Idé, Yusuke Kanehira, Rinju Yohda, Takeshi Ueno, Akira Tajima, Toshiya Watanabe
2012 J jnl
Modeling Patent Quality: A System for Large-scale Patentability Analysis using Text Mining.
J. Inf. Process.
Shohei Hido, Shoko Suzuki, Risa Nishiyama, Takashi Imamichi, Rikiya Takahashi, Tetsuya Nasukawa, Tsuyoshi Idé, Yusuke Kanehira, Rinju Yohda, Takeshi Ueno, Akira Tajima, Toshiya Watanabe
2010 J jnl
A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura
2008 J jnl
1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura
2008 J jnl
55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers.
IEICE Trans. Electron.
Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
2008 C conf
An area-efficient sampling rate converter using negative feedback technique.
ISCAS
Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura
2007 J jnl
A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
2006 J jnl
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers.
IEEE J. Solid State Circuits
Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
2006 — conf
A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters.
CICC
Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura
2006 C conf
Balanced 3-phase analog signal processing for radio communications.
ISCAS
Takafumi Yamaji, Tetsuro Itakura, Rui Ito, Takeshi Ueno, Hidenori Okuni
2006 J jnl
Low-Power Design of 10-bit 80-MSPS Pipeline ADCs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
2005 — conf
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers.
ESSCIRC
Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
2005 J jnl
A 0.9 V 1.5 mW Continuous-Time Modulator for W-CDMA.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takeshi Ueno, Tetsuro Itakura
2005 — conf
A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOS.
CICC
Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
2005 J jnl
A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter.
IEICE Electron. Express
Tomohiko Ito, Takeshi Ueno, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura
2002 J jnl
A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching.
IEEE J. Solid State Circuits
Takeshi Ueno, Akira Yasuda, Takafumi Yamaji, Tetsuro Itakura