Takeshi Sakata

14 papers A* 1Journal 12Unranked 1
YearRankTypeTitle / Venue / Authors
2005 J jnl
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router.
IEEE J. Solid State Circuits
Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara
2005 — conf
A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup.
ICC
Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara
1999 J jnl
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.
IEEE J. Solid State Circuits
Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura
1997 J jnl
The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory.
IEEE J. Solid State Circuits
Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya
1995 J jnl
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.
IEEE J. Solid State Circuits
Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda
1995 J jnl
Low-noise, high-speed data transmission using a ringing-canceling output buffer.
IEEE J. Solid State Circuits
Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki
1994 J jnl
Subthreshold-current reduction circuits for multi-gigabit DRAM's.
IEEE J. Solid State Circuits
Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki
1994 J jnl
Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's.
IEEE J. Solid State Circuits
Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki
1993 J jnl
A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays.
IEEE J. Solid State Circuits
Takayuki Kawahara, Takeshi Sakata, Kiyoo Itoh, Yoshiki Kawajiri, Takesada Akiba, Goro Kitsukawa, Masakazu Aoki
1993 J jnl
A single 1.5-V digital chip for a 10
IEEE Trans. Neural Networks
Takao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito
1993 J jnl
Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's.
IEEE J. Solid State Circuits
Masashi Horiguchi, Takeshi Sakata, Kiyoo Itoh
1991 J jnl
A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture.
IEEE J. Solid State Circuits
Katsutaka Kimura, Takeshi Sakata, Kiyoo Itoh, Toru Kaga, Takashi Nishida, Yoshifumi Kawamoto
1990 J jnl
Studies on the structure and stabilizing factor of the CUUCGG hairpin RNA using chemically synthesized oligonucleotides.
Nucleic Acids Res.
Takeshi Sakata, Hidekazu Hiroaki, Yasushi Oda, Toshiki Tanaka, Morio Ikehara, Seiichi Uesugi
1985 A* conf
A circuit comparison system for bipolar linear LSI.
DAC
Takeshi Sakata, Aritoyo Kishimoto